Intel Arria 10 User Manual page 254

Parameter
Number of auxiliary MCGB
clock input ports
MCGB input clock frequency
MCGB output data rate
Bonding
Enable bonding clock output
ports
Enable feedback
compensation bonding
PMA interface width
Dynamic Reconfiguration
Enable dynamic
reconfiguration
Enable Altera Debug Master
Endpoint
Separate avmm_busy from
reconfig_waitrequest
Optional Reconfiguration Logic
Enable capability registers
Set user-defined IP identifier
Enable control and status
registers
Configuration Files
Configuration file prefix
Generate SystemVerilog
package file
Generate C Header file
Generate MIF (Memory
Initialize file)
Generation Options
Generate parameter
documentation file
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
® ®
Intel Arria 10 Transceiver PHY User Guide
254
Gen1 PIPE
N/A for x1
0 for x2, x4, x8
1250MHz
2500Mbps
N/A for x1 design
Enable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
2. Implementing Protocols in Arria 10 Transceivers
Gen2 PIPE
N/A for x1
0 for x2, x4, x8
2500MHz
5000Mbps
N/A for x1 design
Enable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
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Gen3 PIPE (For Gen1/
Gen2 speeds)
N/A for x1
N/A for x2, x4, x8
2500MHz
5000Mbps
N/A for x1
N/A for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable