Intel Arria 10 User Manual page 354

3.1.2.1. Instantiating the ATX PLL IP Core
The Arria 10 transceiver ATX PLL IP core provides access to the ATX PLLs in the
hardware. One instance of the PLL IP core represents one ATX PLL in the hardware.
1. Open the Quartus Prime software.
2. Click Tools
3. In IP Catalog, under Library
Transceiver ATX PLL and click Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The ATX PLL IP core Parameter Editor window opens.
3.1.2.2. ATX PLL IP Core
Table 229. ATX PLL Configuration Options, Parameters, and Settings
Parameter
Message level for rule violations
Protocol mode
Bandwidth
Number of PLL reference clocks
Selected reference clock source
Primary PLL clock output buffer
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Intel Arria 10 Transceiver PHY User Guide
354
IP Catalog.
Transceiver PLL
Range
Error Specifies the messaging level to use for parameter rule
violations.
Warning
•
•
Basic Governs the internal setting rules for the VCO.
PCIe* Gen1 This parameter is not a preset. You must set all other
parameters for your protocol.
PCIe Gen2
PCIe Gen3
SDI_cascade
OTN_cascade
UPI TX
SAS TX
Low Specifies the VCO bandwidth.
Medium Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
High
1 to 5 Specifies the number of input reference clocks for the ATX
PLL.
You can use this parameter for data rate reconfiguration.
0 to 4 Specifies the initially selected reference clock input to the
ATX PLL.
GX clock output Specifies which PLL output is active initially.
buffer
•
GT clock output
buffer
•
3. PLLs and Clock Networks
, select Arria 10
Description
Error—Causes all rule violations to prevent IP
generation.
Warning—Displays all rule violations as warnings and
allows IP generation in spite of violations.
If GX is selected, turn ON "Enable PLL GX clock
output port".
If GT is selected, turn ON "Enable PLL GT clock
output port".
UG-01143 | 2018.06.15
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