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3. PLLs and Clock Networks
UG-01143 | 2018.06.15
•
If you use the ATX PLL, set the following configuration settings:
— Under the Master Clock Generation Block Tab
— Under the Dynamic Reconfiguration Tab
•
If you use the fPLL, set the following configuration settings:
— Under the PLL Tab
— Under the Master Clock Generation Block Tab
— Under the Dynamic Reconfiguration Tab
3. Configure the Native PHY IP core using the IP Parameter Editor
•
Set the Native PHY IP core TX Channel bonding mode to either PMA
bonding or PMA/PCS bonding.
•
Turn ON Enable dynamic reconfiguration
4. Create a top level wrapper to connect the PLL IP cores to Native PHY IP core.
•
In this case, the PLL IP core has
[5:0].
•
The Native PHY IP core has
multiplied by the number of channels in a transceiver bank. (six channels in
the transceiver bank).
•
Unlike the x6/xN bonding mode, for this mode, the PLL should be instantiated
multiple times. (One PLL is required for each transceiver bank that is a part of
the bonded group.) Instantiate a PLL for each transceiver bank used.
•
Connect the
channels in the same transceiver bank.
•
Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of transceiver channels used in the bonding group.
Steps to recalibrate the PLL after power up calibration
1. Dynamic reconfigure the PLL to change the feedback from the master CGB to
feedback from PLL.
•
For ATX PLL, Read-Modify-Write 0x1 to offset address 0x110[2] of the ATX
PLL.
•
For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL.
2. Recalibrate the PLL.
3. After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure
the PLL to change the feedback to master CGB.
•
Enable Include Master Clock Generation Block.
•
Turn ON Enable Bonding Clock output ports.
•
Turn ON Enable feedback compensation bonding.
•
Turn ON Enable dynamic reconfiguration
•
Set the PLL Feedback type to feedback compensation bonding.
•
Turn ON Enable Bonding Clock output ports.
•
Turn ON Enable dynamic reconfiguration
tx_bonding_clocks
tx_bonding_clocks
tx_bonding_clocks
output from each PLL to (up to) six
®
Intel
Arria
output bus with width
input bus with width [5:0]
®
10 Transceiver PHY User Guide
407
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