Intel Arria 10 User Manual page 430

a. Perform dynamic reconfiguration.
b. Deassert
c.
Deassert
you deassert
3. Wait for
tx_analogreset
completed the reset request for deassertion.
4. The
pll_locked
tx_analogreset_ack
5. Deassert
goes high.
Figure 212. Dynamic Reconfiguration of Transmitter Channel During Device Operation
4.3.2.1.4. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
The numbers in this list correspond to the numbers in the "Dynamic Reconfiguration of
Receiver Channel During Device Operation" figure below.
1. Assert
® ®
Intel Arria 10 Transceiver PHY User Guide
430
pll_powerdown
tx_analogreset
pll_powerdown
tx_analogreset_ack
.
tx_analogreset_ack
signal goes high after the TX PLL acquires lock. Wait for
to go low before monitoring the
tx_digitalreset
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
tx_analogreset_ack
pll_powerdown
pll_locked
tx_digitalreset
Note:
(1)
Area in gray is don't care zone.
and
rx_analogreset
after t .
pll_powerdown
. This step can be done at the same time or after
.
to go low, to ensure successful deassertion of
goes low when TRS has successfully
a minimum t
tx_digitalreset
Legal
Reconfiguration
Window
1 2 3 4
while
rx_digitalreset
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
signal.
pll_locked
time after
pll_locked
t
tx_digitalreset
5
is low.
rx_cal_busy