Intel Arria 10 User Manual page 232

Protocol Feature
Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps
signaling rate
Dynamic transmitter margining for differential output voltage
control
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB
Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and
equalization
PCS PMA interface width (bits)
Receiver Electrical Idle Inference (EII)
Related Information
• PCIe Gen3 PCS Architecture
For more information about PIPE Gen3.
• Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 3.0
2.7.2.1. Gen1/Gen2 Features
In a PIPE configuration, each channel has a PIPE interface block that transfers data,
control, and status signals between the PHY-MAC layer and the transceiver channel
PCS and PMA blocks. The PIPE configuration is based on the PIPE 2.0 specification. If
you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in
the FPGA fabric.
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
In a PIPE configuration, Native PHY IP Core provides an input signal
that is functionally equivalent to the RATE signal specified in the PCIe
[1:0]
specification. A change in value from 2'b00 to 2'b01 on this input signal
initiates a data rate switch from Gen1 to Gen2. A change in value from 2'b01
[1:0]
to 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1.
2.7.2.1.2. Transmitter Electrical Idle Generation
The PIPE interface block in Arria 10 devices puts the transmitter buffer in an electrical
idle state when the electrical idle input signal is asserted. During electrical idle, the
transmitter buffer differential and common mode output voltage levels are compliant
with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain
power states.
Note: For more information about input signal levels required in different power states, refer
to Power State Management in the next section.
® ®
Intel Arria 10 Transceiver PHY User Guide
232
2. Implementing Protocols in Arria 10 Transceivers
Gen1
(2.5 Gbps)
No
No
No
No
10
Implement in FPGA
fabric
on page 495
UG-01143 | 2018.06.15
Gen2 Gen3
(5 Gbps) (8 Gbps)
No Yes
Yes Yes
Yes Yes
No Yes
10 32
Implement in Implement in
FPGA fabric FPGA fabric
pipe_rate
pipe_rate