Intel Arria 10 User Manual page 298

Figure 126. TX FIFO Basic Mode Operation
tx_clkout (read side)
tx_coreclk (write side)
tx_parallel_data[63:0]
tx_digitalreset
tx_enh_datavalid
tx_fifo_pfull
For RX FIFO, assert
This can be done with the following example assignment:
assign rx_enh_read_en = ~rx_fifo_pempty;
Figure 127. RX FIFO Basic Mode Operation
rx_clkout (write side)
rx_coreclkin (read side)
rx_parallel_data[63:0]
rx_digitalreset
rx_enh_read_en
rx_fifo_pfull
rx_fifo_empty
If you are using even gear ratios, the
uneven gear ratios,
rx_enh_data_valid
rx_enh_datavalid
Register and Fast Register Mode
This FIFO mode is used for protocols, which require deterministic latency. You can tie
tx_fifo_wr_en
2.9.1.5. TX Data Bitslip
The bit slip feature in the TX gearbox allows you to slip the transmitter bits before
they are sent to the serializer.
The value specified on the TX bit slip bus indicates the number of bit slips. The
minimum slip is one UI. The maximum number of bits slipped is equal to the FPGA
fabric-to-transceiver interface width minus 1. For example, if the FPGA fabric-to-
transceiver interface width is 64 bits, the bit slip logic can slip a maximum of 63 bits.
Each channel has 6 bits to determine the number of bits to slip. The TX bit slip bus is
a level-sensitive port, so the TX serial data is bit slipped statically by TX bit slip port
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Intel Arria 10 Transceiver PHY User Guide
298
64' d 0 64' d 1 64' d 2
tx_fifo_pempty
tx_fifo_full
rx_enh_read_en
64' d 0 64' d 1 64' d 2
rx_fifo_pempty
rx_enh_data_valid
is high. Discard invalid RX parallel data when the
signal is low.
to 1.
2. Implementing Protocols in Arria 10 Transceivers
64' d 3 64' d 4 64' d 5 64' d 6
with the
rx_fifo_pempty
64' d 3 64' d 4 64' d 5 64' d 6
rx_enh_data_valid
toggles. RX parallel data is valid when
UG-01143 | 2018.06.15
64' d 7 64' d 8 64' d 9 64'ha
signal going low.
64' d 7 64' d 8 64' d 9 64'ha
signal is always high. For