Intel Arria 10 User Manual page 388

For configurations that use the byte deserializer block, the clock divided by 2 or 4 is
used by the byte deserializer and the write side of the RX phase compensation FIFO.
Figure 183. Receiver Standard PCS and PMA Clocking
Receiver PMA
All configurations that use the standard PCS channel must have a 0 ppm phase
difference between the receiver datapath interface clock and the read side clock of the
RX phase compensation FIFO.
Figure 184. Receiver Enhanced PCS and PMA Clocking
Receiver PMA
Parallel Clock
Parallel and Serial Clock
The receiver PCS forwards the following clocks to the FPGA fabric:
•
rx_clkout
•
tx_clkout
You can clock the receiver datapath interface using one of the following methods:
• Quartus Prime selected receiver datapath interface clock
• User-selected receiver datapath interface clock
Related Information
Unused or Idle Clock Line Requirements
For more information about unused or idle transceiver clock lines in design.
® ®
Intel Arria 10 Transceiver PHY User Guide
388
Parallel Clock
(Recovered) rx_clkout
tx_clkout
Parallel Clock
PRBS
(From Clock
Verifier
Divider)
Parallel Clock
Serial Clock
Parallel and Serial Clock
Receiver Enhanced PCS
PRBS
Verifier
Serial Clock
— for each receiver channel when the rate matcher is not used.
— for each receiver channel when the rate matcher is used.
3. PLLs and Clock Networks
Receiver Standard PCS
/2, /4
rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
rx_pma_div_clkout
PRP
Verifier
10GBASE-R
BER Checker
on page 389
UG-01143 | 2018.06.15
FPGA
Fabric
rx_coreclkin
rx_clkout or
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
FPGA
Fabric
rx_clkout