Intel Arria 10 User Manual page 127

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Arria 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR
PHY. This provides a coding gain to increase the link budget and BER performance on
a broader set of backplane channels as defined in Clause 69. It provides additional
margin to account for variations in manufacturing and environment conditions. The
additional TX FEC sublayer:
• Receives data from the TX PCS
• Transcodes 64b/66b words
• Performs encoding/framing
• Scrambles and sends the FEC data to the PMA
The RX FEC sublayer:
• Receives data from the PMA
• Performs descrambling
• Achieves FEC framing synchronization
• Decodes and corrects data where necessary and possible
• Recodes 64b/66b words and sends the data to the PCS
The 10GBASE-R with KR FEC protocol is a KR FEC sublayer placed between the PCS
and PMA sublayers of the 10GBASE-R physical layer.
Figure 57. Transceiver Channel Datapath and Clocking for 10GBASE-R with KR FEC
Notes:
1. Value is based on the clock division factor chosen
2. Value is calculated as data rate/FPGA fabric - PCS interface width
3. Value is calculated as data rate/PCS-PMA interface width
4. For 10GBASE-R with KR FEC, TX FIFO is in phase compensation mode
5. For 10GBASE-R with KR FEC, RX FIFO is in 10GBASE-R mode
The CMU PLL or the ATX PLLs generate the TX high speed serial clock.
Transmitter PMA Transmitter Enhanced PCS
64
PRBS
tx_hf_clk
Generator
tx_pma_clk tx_krfec_clk Parallel Clock (161.1 MHz) (3)
Receiver PMA Receiver Enhanced PCS
64
PRBS
Verifier
rx_rcvd_clk
rx_pma_clk rx_krfec_clk
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
64
66
PRP
Generator
KR FEC
tx_pma_div_clkout
rx_pma_div_clkout
PRP
Verifier
Parallel Clock (161.1 MHz) (3)
10GBASE-R
BER Checker
KR FEC
tx_serial_clk0
(5156.25 MHz) =
Data rate/2
Clock Divider
Serial Clock
Parallel and Serial Clocks
® ®
Intel Arria
FPGA
Fabric
TX
Data &
Control
64 + 8
@ 156.25 MHz
from XGMII
tx_clkout
RX
Data &
Control
64 + 8
@ 156.25 MHz
from XGMII
rx_clkout
ATX PLL
fPLL
CMU PLL
Input Reference Clock
10 Transceiver PHY User Guide
127