Intel Arria 10 User Manual page 262

Port
,
rx_datak[3:0] [1:0]
[0]
pipe_rx_sync_hdr[(2N-1)
:0]
pipe_rx_blk_start[(N-1)
:0]
pipe_rx_data_valid[(N-1
):0]
pipe_rx_valid[(N-1):0]
pipe_phy_status[(N-1):
0]
pipe_rx_elecidle[(N-1):
0]
pipe_rx_status[(3N-1):
0]
® ®
Intel Arria 10 Transceiver PHY User Guide
262
Direction Clock Domain
, or
Out
rx_coreclkin
Out
rx_coreclkin
Out
rx_coreclkin
Out
rx_coreclkin
Out
rx_coreclkin
Out
rx_coreclkin
Out Asynchronous
Out
rx_coreclkin
2. Implementing Protocols in Arria 10 Transceivers
Description
The data and control indicator.
For Gen1 or Gen2, when 0, indicates that
rx_parallel_data
indicates that
rx_parallel_data
control.
For Gen3, corresponds to
Bit[0]
rx_parallel_data[7:0]
corresponds to
rx_parallel_data[15:8]
and so on. Refer to tableBit Mappings When
the Simplified Interface is Disabled for more
details.
For Gen3, indicates whether the 130-bit
block being transmitted is a Data or Control
Ordered Set Block. The following encodings
are defined:
2'b10: Data block
2'b01: Control Ordered Set block
This value is read when
pipe_rx_blk_start
Section 4.2.2.1. Lane Level Encoding in the
PCI Express Base Specification, Rev. 3.0 for
a detailed explanation of data transmission
and reception using 128b/130b encoding and
decoding.
For Gen3, specifies the start block byte
location for RX data in the 128-bit block
data. Used when the interface between the
PCS and PHY-MAC (FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data rates.
Active High
For Gen3, this signal is deasserted by the
PHY to instruct the MAC to ignore
rx_parallel_data
A value of 1'b1 indicates the MAC should use
the data. A value of 1'b0 indicates the MAC
should not use the data.
Active High
Asserted when RX data and control are valid.
Signal used to communicate completion of
several PHY requests.
Active High
When asserted, the receiver has detected an
electrical idle.
Active High
Signal encodes receive status and error
codes for the receive data stream and
receiver detection. The following encodings
are defined:
3'b000 - Receive data OK
3'b001 - 1 SKP added
3'b010 - 1 SKP removed
3'b011 - Receiver detected
3'b100 - Either 8B/10B or 128b/130b decode
error and (optionally) RX disparity error
3'b101 - Elastic buffer overflow
3'b110 - Elastic buffer underflow
UG-01143 | 2018.06.15
is data, when 1,
is
,
Bit[1]
,
= 4'b0001. Refer to
for current clock cycle.
continued...