Intel Arria 10 User Manual page 291

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 122. Transceiver Channel Datapath and Clocking for a Basic with KR FEC
Configuration
Clock frequencies in this figure are examples based on a 10.3125 Gbps data rate.
Notes:
1. Value is based on the clock division factor chosen
2. Value is calculated as data rate on parallel interface/FPGA fabric - PCS interface width
3. Value is calculated as data rate on serial interface/PCS-PMA interface width
2.9.1.1. How to Implement the Basic (Enhanced PCS) and Basic with KR FEC
Transceiver Configuration Rules in Arria 10 Transceivers
You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL
architecture, and the reset controller before implementing the Basic (Enhanced PCS)
or Basic with KR FEC Transceiver Configuration Rule.
1. Open the IP Catalog and select the Arria 10 Transceiver Native PHY IP.
Refer to
2. Select Basic (Enhanced PCS) or Basic with KR FEC from the Transceiver
Configuration Rules list located under Datapath Options.
3. Use the parameter values in the tables in
Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules
starting point. Or, you can use the protocol presets described in
PHY
4. Click Finish to generate the Native PHY IP (this is your RTL file).
Transmitter PMA Transmitter Enhanced PCS
64
PRBS
tx_hf_clk
Generator
Parallel Clock (161.13 MHz) (3)
tx_pma_clk tx_krfec_clk
Receiver PMA Receiver Enhanced PCS
PRBS
Verifier
rx_rcvd_clk
/64
rx_pma_clk
rx_krfec_clk
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Select and Instantiate the PHY IP Core
Presets. You can then modify the settings to meet your specific requirements.
PRP
Generator
KR FEC
tx_pma_div_clkout
rx_pma_div_clkout
PRP
Verifier
Parallel Clock (161.13 MHz) (3)
10GBASE-R
BER Checker
KR FEC
tx_serial_clk0
(5156.25 MHz) =
Data rate/2
Clock Divider
Serial Clock
Parallel and Serial Clocks
on page 33 for more details.
Transceiver Native PHY IP Parameters for
® ®
Intel Arria
FPGA
Fabric
TX
Data &
Control
64 + 2
156.25 MHz (2)
tx_clkout
RX
Data &
Control
64 + 2
156.25 MHz (2)
rx_clkout
ATX PLL
fPLL
CMU PLL
Input Reference Clock
as a
Transceiver Native
10 Transceiver PHY User Guide
291