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•
Changed the blocks and clock connections in the "Clocks for Standard and 10G PCS and TX PLLs"
figure.
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Changed signal names and descriptions in the "Clock and Reset Signals" table.
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Changed the parameter name for 10GbE Reference Clock frequency and added the 1G
Reference clock frequency parameter in the "10GBASE-R Parameters" table.
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Removed the Set FEC_ability bit on power up and reset and Set FEC_enable bit on power
up and resetparameters from the "FEC Options" table.
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Updated the list of available signals in the "1G/10GbE PHY Top-Level Signals" figure.
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Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register
Definitions" table.
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Added the 0x4A8 and 0x4A9 addresses and updated the name for address 0x4A2 and 0x4A3 in the
"10GBASE-KR, Backplane, FEC GMII PCS Registers" table.
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Added the Speed Change Summary section.
Made the following changes to the PCI Express section:
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Added a new topic Pipe link equalization for Gen 3 data rate.
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Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Connect
TX PLLs for PIPE Gen1, Gen2 and Gen3 Mode section.
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Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the How to Implement
PCI Express in Arria 10 Transceivers section.
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Changed "MegaWizard Plugin Manager" to "Parameter Editor"/"IP Catalog" in the Supported Pipe
Features section.
Made the following changes to the CPRI section:
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Added new values to each row in the "TX PLL Supported Data Rates" table.
Made the following changes to the Other Protocols section:
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Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.
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Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.
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Changed references from MegaWizard to IP Catalog or Parameters Editor.
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Using the Basic and Basic with KR FEC Configurations of Enhanced PCS
— Updated the "Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)
— Updated the "General and Datapath Parameters", "TX PMA Parameters", "RX PMA Parameters",
— Added the "Equalization" table.
— Added the "How to Enable Low Latency in Basic Enhanced PCS" section.
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Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS
— Updated the values in the "Manual Mode when the PCS-PMA Interface is 8 Bits", "Manual Mode
— Added the "8B/10B Encoder and Decoder" and "8B/10B TX Disparity Control" sections.
— Updated the "Connection Guidelines for a Basic/Custom Design" figure.
— Updated the "General and Datapath Options Parameters", "TX PMA Parameters", "RX PMA
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Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels
— Updated the maximum data rate for GT channels to 25.4 Gbps.
— Added information about PCS Direct mode.
— Updated "ATX PLL IP with GT Clock Lines Enabled" figure.
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Updated the How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in
Arria 10 Transceivers section.
Made the following changes to the Simulating the Transceiver Native PHY IP Core section:
•
Updated the "How to Use NativeLink to Specify a ModelSim Simulation" section.
•
Updated the "NativeLink Generated Scripts for Third-Party RTL Simulation" table.
2013.12.02
Initial release.
®
®
Intel
Arria
10 Transceiver PHY User Guide
346
Configuration" figure and added footnote 3.
and "Enhanced PCS Parameters" tables.
when the PCS-PMA Interface is 10 Bits", and "Manual Mode when the PCS-PMA Interface is 16
Bits" figures.
Parameters", and "Standard PCS Parameters" tables.
2. Implementing Protocols in Arria 10 Transceivers
Changes
UG-01143 | 2018.06.15
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