Intel Arria 10 User Manual page 121

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 91. General and Datapath Options
The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general
and datapath options to customize the transceiver.
Message level for rule violations
Transceiver configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Table 92. TX PMA Parameters
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port
tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Enable tx_pma_qpipulldn port (QPI)
Enable tx_pma_txdetectrx port (QPI)
Enable tx_pma_rxfound port (QPI)
Enable rx_seriallpbken port
Table 93. RX PMA Parameters
Number of CDR reference Clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
Parameter
Parameter
Parameter
Value
error
warning
GbE (for GbE)
GbE 1588 (for GbE with IEEE 1588v2)
TX/RX Duplex
TX Simplex
RX Simplex
1 to 96
1250 Mbps
On/Off
On/Off
Value
Not bonded
1, 2, 4, 8
1, 2, 3, 4
0 to 3
On/Off
On/Off
Disabled, 1, 2, 33, 40, 66
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Value
1 to 5
0 to 4
Select legal range defined by the Quartus Prime
software
100, 300, 500, 1000
manual
® ®
Intel Arria 10 Transceiver PHY User Guide
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