Intel Arria 10 User Manual page 436

Name
Separate interface per
channel/PLL
Enable TX PLL reset control
pll_powerdown duration
Synchronize reset input for PLL
powerdown
Enable TX channel reset control
Use separate TX reset per channel
TX digital reset mode
tx_analogreset duration
tx_digitalreset duration
pll_locked input hysteresis
® ®
Intel Arria 10 Transceiver PHY User Guide
436
Range
On /Off
TX PLL
On /Off
1-999999999
On /Off
TX Channel
On /Off
On /Off
Auto, Manual, Expose
Port
1-999999999
1-999999999
0-999999999
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Description
When On, the Transceiver PHY Reset Controller
provides a separate reset interface for each
channel and PLL.
When On, the Transceiver PHY Reset Controller IP
core enables the reset control of the TX PLL. When
Off, the TX PLL reset control is disabled.
Specifies the duration of the PLL powerdown period
in ns. The value is rounded up to the nearest clock
cycle. The default value is 1000 ns.
When On, the Transceiver PHY Reset Controller
synchronizes the PLL powerdown reset with the
Transceiver PHY Reset Controller input clock. When
Off, the PLL powerdown reset is not synchronized.
When On, the Transceiver PHY Reset Controller
enables the control logic and associated status
signals for TX reset. When Off, disables TX reset
control and status signals.
When On, each TX channel has a separate reset.
When Off, the Transceiver PHY Reset Controller
uses a shared TX reset controller for all channels.
Specifies the Transceiver PHY Reset Controller
behavior when the
pll_locked
deasserted. The following modes are available:
•
Auto—The associated
tx_digitalreset
controller automatically resets whenever the
signal is deasserted. Intel
pll_locked
recommends this mode.
•
Manual—The associated
tx_digitalreset
controller is not reset when the
signal is deasserted, allowing you to choose
corrective action.
• Expose Port—The
tx_manual
level signal of the IP core. You can dynamically
change this port to Auto or Manual. (1=
Manual , 0 = Auto)
Specifies the time in ns to continue to assert
after the reset input and all
tx_analoglreset
other gating conditions are removed. The value is
rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings
preset.
Specifies the time in ns to continue to assert the
after the reset input and all
tx_digitalreset
other gating conditions are removed. The value is
rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings
preset. The default value for Model 2 is 20
ns.
Specifies the amount of hysteresis in ns to add to
the status input to filter spurious
pll_locked
unreliable assertions of the
pll_locked
signal is
pll_locked
signal is a top-
signal. A
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