Intel Arria 10 User Manual page 339

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Document
Version
• Added parameter "Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE"
in "Dynamic Reconfiguration" table.
• Added parameter "Include PMA analog settings in configuration Files"in "Configuration Files".
• Added "Analog PMA Settings (Optional) in Dynamic Reconfiguration" tabl.e
Made the following changes to the 1G/10 Gbps Ethernet PHY IP Core section:
• Changed the release date and version in the "1G/10GbE Release Information" table.
• Changed the descriptions for
Reset Signals" table.
• Changed descriptions in the "General Options Parameters" table.
• Added the "1G Data Mode" table to the PMA Registers section.
• Removed the "1G Data Mode" rows from the Arria 10 GMII PCS Registers section.
Made the following changes to the 10GBASE-KR PHY IP Core with FEC Option section:
• Added bit 12 to the 0x4B0 word address in the "10GBASE-KR Register Definitions" table.
Made the following changes to the Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 section:
• Added a note to the "Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with
IEEE 1588v2" figure.
• Changed the note in the "Gigabit Ethernet (GbE) and GbE with IEEE 1588v2" section.
• Changed some signal names in the "Signals and Ports for Native PHY IP Configured for GbE or GbE
with IEEE 1588v2" figure.
• Changed the values in the "TX PMA Parameters" table.
• Added a parameter to and updated values in the "RX PMA Parameters" table.
• Changed the values in the "Standard PCS Parameters" table.
Made the following changes to the 10GBASE-R section:
• Added description text to the "10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with
FEC Variants" section.
• Changed steps in the "How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers" section.
• Changed signal names in the "Signals and Ports of Native PHY IP Core for the 10GBASE-R,
10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.
• Updated parameters in the "General and Datapath Parameters" table.
• Updated parameters in the "RX PMA Parameters" table.
• Updated parameters in the "Enhanced PCS Parameters" table.
• Updated parameters in the "Block Sync Parameters" table.
• Updated parameters in the "Dynamic Reconfiguration Parameters" table.
Made the following changes to the XAUI PHY IP Core section:
• Changed the release date and version in the "XAUI Release Information" table.
• Changed the descriptions in the "XAUI PHY IP Core Registers" table.
• Added description in the "XAUI PHY IP Core" section.
Made the following changes to the 1G/2.5G/10G Multi-rate Ethernet PHY IP Core section:
• Added this section.
Made the following changes to the PCI Express (PIPE) section:
• Updated description for port "pipe_g3_txdeemph[17:0]" in the "Ports for Arria 10 Transceiver
Native PHY in PIPE Mode" table.
• Updated "Ports for Arria 10 Transceiver Native PHY in PIPE Mode" table for presets to TX De-
emphasis mappings.
• Updated x4 Configuration and x4 Alternate Configuration figures in the "Master Channel in Bonded
Configurations section".
• Updated "PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate" section.
• Updated "Connection Guidelines for a PIPE Gen3 Design" figure.
• Added recommendations in the "How to Implement PCI Express (PIPE) in Arria 10 Transceivers"
section.
• Updated description of parameter "PCS TX channel bonding master" in the "Parameters for Arria 10
Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA" table.
• Added table "Parameter Settings for Arria 10 fPLL IP in PIPE Gen1, Gen2, Gen3 modes" in the "fPLL
IP Parameter Settings for PIPE" section.
Changes
and
tx_serial_clk_1g rx_cdr_refclk_1g
Intel
in the "Clock and
continued...
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Arria 10 Transceiver PHY User Guide
339