Intel Arria 10 User Manual page 84

Table 61. Bit Encodings for Basic Double Width Mode
For basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header.
Name Bit
[1:0]
tx_control
[8:2]
[10:9]
[17:11]
Table 62. Bit Encodings for Basic Mode
In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Name Bit
[1:0]
tx_control
[2]
Enhanced PCS RX Control Port Bit Encodings
Table 63. Bit Encodings for Interlaken
Name
[1:0]
rx_control
[2]
[3]
[4]
[5]
[6]
[7]
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Intel Arria 10 Transceiver PHY User Guide
84
Functionality
Synchronous header
Unused
Synchronous header
Unused
Functionality
Synchronous header
Inversion control
Bit Functionality
Synchronous header
Inversion control
Payload word location
Synchronization word location
Scrambler state word location
SKIP word location
Diagnostic word location
2. Implementing Protocols in Arria 10 Transceivers
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
A logic low indicates that built-in disparity
generator block in the Enhanced PCS maintains
the running disparity.
The value 2'b01 indicates a data
word. The value 2'b10 indicates a
control word.
A logic low indicates that the built-
in disparity generator block in the
Enhanced PCS maintains the
Interlaken running disparity. In the
current implementation, this bit is
always tied logic low (1'b0).
A logic high (1'b1) indicates the
payload word location in a
metaframe.
A logic high (1'b1) indicates the
synchronization word location in a
metaframe.
A logic high (1'b1) indicates the
scrambler word location in a
metaframe.
A logic high (1'b1) indicates the
SKIP word location in a metaframe.
A logic high (1'b1) indicates the
diagnostic word location in a
metaframe.
UG-01143 | 2018.06.15
Description
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