Intel Arria 10 User Manual page 171

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Note: You might observe timing violations. If the timing path is within the IP, you can ignore
these violations. This will be fixed in a future release of the Intel Quartus Prime
software.
Related Information
• Using the Arria 10 Transceiver Native PHY IP Core
• General Options
• 10GBASE-R Parameters
• 10M/100M/1Gb Ethernet Parameters
• Speed Detection Parameters
• PHY Analog Parameters
2.6.4.5.1. General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 130. General Options Parameters
Parameter Name
Enable internal PCS
reconfiguration logic
Enable IEEE 1588 Precision
Time Protocol
Enable M20K block ECC
protection
Enable tx_pma_clkout port
Enable rx_pma_clkout port
Enable tx_divclk port
Enable rx_divclk port
Enable tx_clkout port
Enable rx_clkout port
Enable Hard PRBS support
and ADME support
on page 139
on page 140
on page 142
on page 173
Options
On
This parameter is only an option when
set to 0, it does not include the reconfiguration module or
Off
expose the
to 1, it provides a simple interface to initiate reconfiguration
between 1G and 10G modes.
On When you turn on this parameter, you enable the IEEE 1588
Precision Time Protocol logic for both 1G and 10G modes.
Off
On When you turn on this parameter, you enable error correction
code (ECC) support on the embedded Nios CPU system. This
Off
parameter is only valid for the backplane variant.
On
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
Off
more information about this port.
On When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
Off
more information about this port.
On
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
Off
more information about this port.
On
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
Off
more information about this port.
On
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
Off
more information about this port.
On
When you turn on this parameter, the
enabled. Refer to the Clock and Reset Interfaces section for
Off
more information about this port.
On When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
Off
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
on page 45
on page 172
Description
or
start_pcs_reconfig
® ®
Intel Arria 10 Transceiver PHY User Guide
= 0. When
SYNTH_SEQ
ports. When set
rc_busy
port is
tx_pma_clkout
port is
rx_pma_clkout
port is
tx_divclk
port is
rx_divclk
port is
tx_clkout
port is
rx_clkout
continued...
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