Intel Arria 10 User Manual page 211

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Signal Name
gmii16b_tx_latency
RX GMII signals—synchronous to
gmii16b_rx_d
gmii16b_rx_err
gmii16b_rx_dv
gmii16b_rx_latency
2.6.5.4.4. XGMII Signals
The XGMII supports 10GbE at 156.25 MHz.
Table 161. XGMII Signals
Signal Name
TX XGMII signals—synchronous to
xgmii_tx_data
xgmii_tx_control
Direction Width
Output 22
rx_clkout
Output 16
Output 2
Output 2
Output 22
Direction Width
xgmii_tx_coreclkin
Input 64, 32
Input 8, 4
Description
The latency of the PHY excluding the PMA block on
the TX datapath:
• Bits [21:10]: The number of clock cycles.
• Bits [9:0]: The fractional number of clock
cycles.
This signal is available when only the Enable IEEE
1588 Precision Time Protocol parameter is
selected.
RX data to the MAC. The PHY sends the lower byte
first followed by the upper byte. Rate matching is
done by the PHY on the RX data from the RX
recovered clock to
rx_clkout
When asserted, indicates an error. Bit[0]
corresponds to
gmii16b_rx_err
corresponds to
gmii16b_rx_err
The bits can be asserted at any time during a
frame transfer to indicate an error in the current
frame.
When asserted, indicates the start of a new frame.
Bit[0] corresponds to
gmii16b_rx_d
corresponds to
gmii16b_rx_d
This signal remains asserted until the PHY sends
the last byte of the data frame.
The latency of the PHY excluding the PMA block on
the RX datapath:
• Bits [21:10]: The number of clock cycles.
• Bits [9:0]: The fractional number of clock
cycles.
This signal is available only when the Enable IEEE
1588 Precision Time Protocol parameter is
selected.
Description
TX data from the MAC. The MAC sends the data in
the following order: bits[7:0], bits[15:8], and so
forth.
The width is:
• 64 bits for 1G/2.5G/10G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations.
TX control from the MAC:
•
[0] corresponds to
xgmii_tx_control
[7:0]
xgmii_tx_data
•
[1] corresponds to
xgmii_tx_control
[15:8]
xgmii_tx_data
• and so forth.
The width is:
® ®
Intel Arria 10 Transceiver PHY User Guide
.
[7:0]; bit[1]
[15:8].
[7:0]; bit[1]
[15:8].
continued...
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