Intel Arria 10 User Manual page 177

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Signal Name
xgmii_tx_dc[61:54]
xgmii_tx_dc[62]
xgmii_tx_dc[70:63]
xgmii_tx_dc[71]
Table 138. RX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name
xgmii_rx_dc[7:0]
xgmii_rx_dc[8]
xgmii_rx_dc[16:9]
xgmii_rx_dc[17]
xgmii_rx_dc[25:18]
xgmii_rx_dc[26]
xgmii_rx_dc[34:27]
xgmii_rx_dc[35]
xgmii_rx_dc[43:36]
xgmii_rx_dc[44]
xgmii_rx_dc[52:45]
xgmii_rx_dc[53]
xgmii_rx_dc[61:54]
xgmii_rx_dc[62]
xgmii_rx_dc[70:63]
xgmii_rx_dc[71]
2.6.4.6.4. GMII Interface
The GMII interface signals drive data to and from the PHY.
Table 139. GMII Interface Ports
Signal Name
gmii_tx_d[7:0]
gmii_tx_en
gmii_tx_err
gmii_rx_d[7:0]
gmii_rx_dv
SDR XGMII Signal Name
xgmii_sdr_data[55:48]
xgmii_sdr_ctrl[6]
xgmii_sdr_data[63:56]
xgmii_sdr_ctrl[7]
XGMII Signal Name
xgmii_sdr_data[7:0]
xgmii_sdr_ctrl[0]
xgmii_sdr_data[15:8]
xgmii_sdr_ctrl[1]
xgmii_sdr_data[23:16]
xgmii_sdr_ctrl[2]
xgmii_sdr_data[31:24]
xgmii_sdr_ctrl[3]
xgmii_sdr_data[39:32]
xgmii_sdr_ctrl[4]
xgmii_sdr_data[47:40]
xgmii_sdr_ctrl[5]
xgmii_sdr_data[55:48]
xgmii_sdr_ctrl[6]
xgmii_sdr_data[63:56]
xgmii_sdr_ctrl[7]
Direction
Input Data to be encoded and sent to the link partner. This signal
is clocked with
Input
The GMII TX control signal. Synchronous to
Input
The GMII TX error signal. Synchronous to
Output Data to be encoded and sent to the link partner. This signal
is clocked with
Output
The GMII RX control signal. Synchronous to
Description
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
Description
Lane 0 data
Lane 0 control
Lane 1 data
Lane 1 control
Lane 2 data
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control
Lane 5 data
Lane 5 control
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
Description
.
tx_clkout
tx_clkout
tx_clkout
.
tx_clkout
tx_clkout
® ®
Intel Arria 10 Transceiver PHY User Guide
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