Intel Arria 10 User Manual page 123

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
RX rate match insert / delete +ve pattern (hex)
Enable rx_std_rmfifo_full port
Enable rx_std_rmfifo_empty port
PCI Express Gen3 rate match FIFO mode
Enable TX bit slip
Enable tx_std_bitslipboundarysel port
RX word aligner mode
RX word aligner pattern length
RX word aligner pattern (hex)
Number of word alignment patterns to achieve sync
Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable tx_polinv port
Enable RX bit reversal
Enable rx_std_bitrev_ena port
Enable RX byte reversal
Enable rx_std_byterev_ena port
Enable RX polarity inversion
Enable rx_polinv port
Enable rx_std_signaldetect port
All options under PCIe Ports
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
Parameters Value
(/K28.5/D16.2/) (for GbE)
0x000a257c
(disabled for GbE with IEEE
0x00000000
1588v2)
On/Off
(option disabled for GbE with IEEE 1588v2)
On/Off
(option disabled for GbE with IEEE 1588v2)
Bypass
Off
On/Off
Synchronous state machine
7
(Comma) (for 7-bit
0x000000000000007c
aligner pattern length),
0x000000000000017c
(/K28.5/) (for 10-bit aligner pattern length)
3
3
3
On/Off
Off
Off
Off
Off
Off
Off
On/Off
On/Off
Off
Off
Off
Off
On/Off
On/Off
On/Off
Off
on page 45
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Intel Arria 10 Transceiver PHY User Guide
123