Intel Arria 10 User Manual page 12

Figure 3. Arria 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard
IP Blocks.
GXBL1H
GXBL1G
GXBL1F
GXBL1E
GXBL1D
GXBL1C
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with "C".
(2) Nomenclature of right column bottom transceiver banks may end with "C", "D", or "E".
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 72 transceiver channels and four PCIe Hard IP blocks.
Arria 10 GX device with 48 transceiver channels and four PCIe Hard IP blocks.
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Intel Arria 10 Transceiver PHY User Guide
12
GX 115 SF45
GX 090 SF45
Transceiver Transceiver
Bank Bank
Transceiver Transceiver
Bank Bank
Transceiver Transceiver
PCIe
Bank Bank
Gen1 - Gen3
Hard IP
Transceiver Transceiver
GX 115 NF45
Bank Bank
GX 090 NF45
Transceiver Transceiver
PCIe
Bank Bank
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver Transceiver
Bank Bank
(1)
1. Arria
Transceiver
GXBR4H
Bank
Transceiver
GXBR4G
Bank
Transceiver
PCIe
GXBR4F
Bank
Gen1 - Gen3
Hard IP
Transceiver
GXBR4E
Bank
Transceiver
PCIe
GXBR4D
Bank
Gen1 - Gen3
Hard IP
Transceiver
GXBR4C
Bank
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10 Transceiver PHY Overview
UG-01143 | 2018.06.15
CH5
CH4
CH3
Transceiver
CH2
Bank
CH1
CH0
(2)