Intel Arria 10 User Manual page 355

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Parameter
Enable PLL GX clock output port
Enable PCIe clock output port
Enable ATX to FPLL cascade clock
output port
Enable fref and clklow port
PLL output frequency
PLL integer reference clock
frequency
Multiply factor (M-Counter)
Divide factor (N-Counter)
Divide factor (L-Counter)
Predivide factor (L-Cascade
Predivider)
Fractional multiply factor (K)
Table 230. ATX PLL—Master Clock Generation Block Parameters and Settings
Parameter
Include Master Clock Generation
(53)
Block
(51)
You can enable both the GX clock output port and the GT clock output port. However, only one
port can be in operation at any given time. You can switch between the two ports using PLL
reconfiguration.
(52)
The fPLL and
fref
detection logic.
(53)
Manually enable the MCGB for bonding applications.
Range
(51)
On/Off
On/Off
On/Off
(52)
. On/Off
Refer to Intel
Arria 10 Device
Datasheet .
Refer to the GUI
Read only
For
OTN_cascade or
SDI_cascade,
refer to the GUI.
Read only
For
SDI_cascade or
OTN_cascade,
refer to the GUI.
Read only
Refer to the GUI
Read only
Range
On/Off
signals should only be used with the Intel external soft lock
clklow
Description
Enables the GX output port which feeds x1 clock lines.
You must select this parameter for PLL output frequency
less than 8.7 GHz, or if you intend to reconfigure the PLL to
a frequency below 8.7 GHz.
Turn ON this port if GX is selected in the "Primary PLL
clock output buffer".
Exposes the
pll_pcie_clk
The port should be connected to the
port.
Enables the ATX to FPLL cascade clock output port.
Enables and ports for external lock detector.
fref clklow
Use this parameter to specify the target output frequency
for the PLL.
Selects the input reference clock frequency for the PLL.
Displays the M-counter value.
Specifies the M-counter value (In SDI_cascade or
OTN_cascade Protocol mode only).
Displays the N-counter value.
For SDI_cascade or OTN_cascade, refer to the GUI.
Displays the L-counter value.
Specifies the L-cascade predivider value. This value must be
2 for a VCO frequency greater than 10.46 GHz and 1 for a
VCO frequency less than 10.46GHz. (In SDI_cascade or
OTN_cascade Protocol mode only).
Displays the actual K-counter value. This parameter is only
available in fractional mode.
Description
When enabled, includes a master CGB as a part of the ATX
PLL IP core. The PLL output drives the Master CGB.
® ®
Intel Arria
port used for PCI Express.
pipe_hclk_input
continued...
10 Transceiver PHY User Guide
355