Intel Arria 10 User Manual page 83

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
• Transceiver PHY Reset Controller Interfaces
2.4.9.1. Enhanced PCS TX and RX Control Ports
This section describes the
protocol configurations.
When Enable simplified data interface is ON, all of the unused ports shown in the
tables below, appear as a separate port. For example: It appears as
unused_tx_control
Enhanced PCS TX Control Port Bit Encodings
Table 58. Bit Encodings for Interlaken
Name Bit
[1:0]
tx_control
[2]
[7:3]
[8]
[17:9]
Table 59. Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC
Name
tx_control
Table 60. Bit Encodings for Basic Single Width Mode
For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Name Bit
[1:0]
tx_control
[17:2]
tx_control
/
unused_rx_control
Functionality
Synchronous header
Inversion control
Unused
Insert synchronous header error or
CRC32
Unused
Bit
[0]
XGMII control signal for
[1]
XGMII control signal for
[2]
XGMII control signal for
[3]
XGMII control signal for
[4]
XGMII control signal for
[5]
XGMII control signal for
[6]
XGMII control signal for
[7]
XGMII control signal for
[17:8] Unused
Functionality
Synchronous header
Unused
on page 437
and bit encodings for different
rx_control
port.
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
A logic low indicates that the built-in disparity
generator block in the Enhanced PCS maintains
the Interlaken running disparity.
You can use this bit to insert synchronous header
error or CRC32 errors. The functionality is similar
to . Refer to
tx_err_ins
description for more details.
Functionality
parallel_data[7:0]
parallel_data[15:8]
parallel_data[23:16]
parallel_data[31:24]
parallel_data[39:32]
parallel_data[47:40]
parallel_data[55:48]
parallel_data[63:56]
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
® ®
Intel Arria 10 Transceiver PHY User Guide
signal
tx_err_ins
83