Intel Arria 10 User Manual page 100

Figure 33. TX Soft Bonding Flow
The following figure shows that after deasserting
logic starts filling the TX FIFO until all lanes are full.
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Intel Arria 10 Transceiver PHY User Guide
100
2. Implementing Protocols in Arria 10 Transceivers
Exit from
tx_digitalreset
Deassert all lanes tx_enh_frame_burst_en
Assert all lanes tx_enh_data_valid
All lanes
full?
yes
Deassert all lanes
tx_enh_data_valid
Any lane
no
send new frame?
tx_enh_frame
asserted?
yes
Wait for extra 16
tx_coreclkin cycles
no
All lanes
full?
yes
TX FIFO pre-fill
completed
tx_digitalreset
UG-01143 | 2018.06.15
no
, TX soft bonding