Intel Arria 10 User Manual page 501

5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
Document
Version
Made the following changes to the PMA Architecture section:
• Added 2nd post-tap and pre-tap Pre-Emphasis signals .
• Updated DFE and CTLE modes of operation and Use Models.
• Added new sections on How to Enable CTLE and How to Enable DFE.
• Changed max data rate for GT channels to 25.8 Gbps in the Receiver Buffer CTLE section.
• Updated Receiver Buffer figure by adding and modifying Adaptive Parametric Tuning Engine to
include CDR and DFE.
• Updated VGA section that includes VGA Frequency response for different gain settings.
2013.12.02 Initial release.
Changes
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Intel Arria 10 Transceiver PHY User Guide
501