Intel Arria 10 User Manual page 256

Parameter
Number of auxiliary MCGB clock input
ports
MCGB input clock frequency
MCGB output data rate
Bonding
Enable bonding clock output ports
Enable feedback compensation bonding
PMA interface width
Dynamic Reconfiguration
Enable dynamic reconfiguration
Enable Altera Debug Master Endpoint
Separate avmm_busy from
reconfig_waitrequest
Optional Reconfiguration Logic
Enable capability registers
Set user-defined IP identifier
Enable control and status registers
Configuration Files
Configuration file prefix
Generate SystemVerilog package file
Generate C Header file
Generate MIF (Memory Initialize file)
Generation Options
Generate parameter documentation file
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
® ®
Intel Arria 10 Transceiver PHY User Guide
256
2. Implementing Protocols in Arria 10 Transceivers
Gen1 PIPE
N/A for x1 N/A for x1
0 for x2, x4, x8 0 for x2, x4, x8
1250 MHz 2500 MHz
2500 Mbps 5000 Mbps
N/A for x1 N/A for x1
Enable for x2, x4, x8 Enable for x2, x4, x8
N/A for x1 design N/A for x1 design
Disable for x2, x4, x8 Disable for x2, x4, x8
N/A for x1 design N/A for x1 design
10 for x2, x4, x8 10 for x2, x4, x8
Disable Disable
Disable Disable
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
N/A N/A
Enable Enable
UG-01143 | 2018.06.15
Gen2 PIPE Gen3 PIPE (For Gen3
N/A for x1
1 for x2, x4, x8
4000 MHz
8000 Mbps
N/A for x1
Enable for x2, x4, x8
Disable for x1
Disable for x2, x4, x8
N/A for x1
10 for x2, x4, x8
Disable
Disable
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Enable
on page 45
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