Intel Arria 10 User Manual page 478

Figure 249. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
rx_parallel_data[79:0]
rx_parallel_data[79:0]
Figure 250. OS Word Deletion
This figure shows the deletion of Ordered set words in the receiver data stream.
Before Deletion
rx_parallel_data[79:0]
FD000000000004AEh
After Deletion
rx_parallel_data[79:0]
FD000000000004AEh
Idle Insertion
Idle insertion occurs in groups of 8 Idles when the
deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of
8 bytes. Data shifting is not necessary. There is a synchronous status
rx_enh_fifo_insert
Table 258. Cases Where Two Idle Words are Inserted
In this table X=don't care, S=start, OS=order set, I-DS=idle in data stream, and I-In=idle inserted. In cases 3
and 4, the Idles are inserted between the LW and UW.
Case
1
2
3
4
Figure 251. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
rx_parallel_data[79:0]
rx_parallel_data[79:0]
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Intel Arria 10 Transceiver PHY User Guide
478
Before Deletion
00000000000004ADh 00000000000004AEh
After Deletion
00000000000004ADh 00000000000004AEh
DDDDDD9CDDDDDD9Ch
000000FBDDDDDD9Ch
signal that is attached to the 8-byte Idles being inserted.
Word Input
UW I-DS
LW X
UW OS
LW X
UW S
LW I-DS
UW S
LW OS
Before Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch
After Insertion
FD000000000004AEh BBBBBB9CDDDDDD9Ch
5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
0707070707FD0000h 000000FB07070707h
AAAAAAAA000000FBh
0707070707FD0000h
Idle Deleted
00000000000000FBh
AAAAAAAA00000000h
OS Deleted
rx_enh_fifo_pempty
Output
I-DS
X
OS
X
I-In
I-DS
I-In
OS
00000000000000FBh AAAAAAAAAAAAAAAAh
0707070707070707h 00000000000000FBh
Idle Inserted
AAAAAAAAAAAAAAAAh
00000000AAAAAAAAh
flag is
I-In
I-In
I-In
I-In
S
I-In
S
I-In