Intel Arria 10 User Manual page 537

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
The following figure shows the signals available when the Native PHY is configured for
four channels and the Share reconfiguration interface option is not enabled.
Figure 277. Signals Available with Independent Native PHY Reconfiguration Interfaces
Table 281. Reconfiguration Interface Ports with Independent Native PHY
Reconfiguration Interfaces
The reconfiguration interface ports when Share reconfiguration interface is disabled. <N> represents the
number of channels.
Port Name
reconfig_clk[N-1:0]
reconfig_reset[N-1:0]
reconfig_write[N-1:0]
reconfig_read[N-1:0]
reconfig_address[N*10-1:0]
reconfig_writedata[N*32-1:0]
reconfig_readdata[N*32-1:0]
reconfig_waitrequest[N-1:0]
reconfig_clk[3:0]
reconfig_reset[3:0]
reconfig_write[3:0]
reconfig_read[3:0]
reconfig_address[39:0]
reconfig_writedata[127:0]
reconfig_readdata[127:0]
reconfig_waitrequest[3:0]
Direction Clock Domain
Input N/A
Input
reconfig_clk
Input
reconfig_clk
Input
reconfig_clk
Input
reconfig_clk
Input
reconfig_clk
Output
reconfig_clk
Output
reconfig_clk
Native PHY IP Core
clk
reset
write
read
address
writedata
readdata
waitrequest
Description
Avalon clock for each channel. The clock
frequency is 100-125 MHz.
Resets the Avalon interface for each channel.
Asynchronous to assertion and synchronous to
deassertion.
Write enable signal for each channel. Signal is
active high.
Read enable signal for each channel. Signal is
active high.
A 10-bit address bus for each channel.
A 32-bit data write bus for each channel. Data
to be written into the address indicated by the
corresponding address field in
.
reconfig_address
A 32-bit data read bus for each channel. Valid
data is placed on this bus after a read
operation. Signal is valid after
goes high and then low.
A one-bit signal for each channel that
indicates the Avalon interface is busy. Keep
the Avalon command asserted until the
interface is ready to proceed with the read/
write transfer. The behavior of this signal
depends on whether the feature Separate
reconfig_waitrequest from the status of
AVMM arbitration with PreSICE is enabled
or not. For more details, refer to the
Arbitration section.
® ®
Intel Arria 10 Transceiver PHY User Guide
waitrequest
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