Intel Arria 10 User Manual page 118

Figure 50. Rate Match FIFO Full Condition
tx_parallel_data 2D
rx_parallel_data 03
rx_std_rmfifo_full
The rate match FIFO does not insert code groups to overcome the FIFO empty
condition. It asserts the
cycles to indicate that the rate match FIFO is empty. The following figure shows the
rate match FIFO empty condition when the read pointer is faster than the write
pointer.
Figure 51. Rate Match FIFO Empty Condition
tx_parallel_data 1E
rx_parallel_data 44
rx_std_rmfifo_empty
In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset
Related Information
Rate Match FIFO
2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing the GbE protocol.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
® ®
Intel Arria 10 Transceiver PHY User Guide
118
2E 2F 30
04 05 06
The rx_std_rmfifo_full status flag indicates
that the FIFO is full at this time
rx_std_rmfifo_empty
1F 20 21 22
45 46 47 48
signal to reset the receiver PCS blocks.
on page 491
2. Implementing Protocols in Arria 10 Transceivers
31 32 33
07 08 09
flag for at least two recovered clock
23 24 25 26
49 4A 4B 4C
The rx_std_rmfifo_empty status flag indicates
that the FIFO is empty at this time
UG-01143 | 2018.06.15
34 35 36
0A 0B 0C
27 28 29 2A
4D 4E 4F 50
37 38
0D 0E
2B 2C 2D
00 01 02