Intel Arria 10 User Manual page 439

4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Signal Name
rx_manual[<n> -1:0]
clock
reset
tx_digitalreset[<n>-1
:0]
tx_analogreset[<n>-1:
0]
tx_ready[<n>-1:0]
rx_digitalreset[<n>
-1:0]
Direction Clock Domain
Input Asynchronous
Input N/A
Input Asynchronous
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Description
logic does not automatically respond to deassertion of
the signal. However, the initial
pll_locked
sequence still requires a one-time
tx_digitalreset
rising edge on before proceeding. When
pll_locked
deasserted, the associated
tx_digitalreset
controller automatically begins its reset sequence
whenever the selected
pll_locked
deasserted.
This optional signal places
rx_digitalreset
controller under automatic or manual control. In
manual mode, the
rx_digitalreset
not respond to the assertion or deassertion of the
signal. The
rx_is_lockedtodata
controller asserts
rx_digitalreset
the signal is asserted.
rx_is_lockedtodata
A free running system clock input to the Transceiver
PHY Reset Controller from which all internal logic is
driven. If a free running clock is not available, hold
reset until the system clock is stable.
Asynchronous reset input to the Transceiver PHY Reset
Controller. When asserted, all configured reset outputs
are asserted. Holding the reset input signal asserted
holds all other reset outputs asserted. An option is
available to synchronize with the system clock. In
synchronous mode, the reset signal needs to stay
asserted for at least (2) clock cycles by default.
Digital reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when any of the following conditions is true:
•
is asserted
reset
•
is asserted
pll_powerdown
•
is asserted
pll_cal_busy
•
is asserted
tx_cal_busy
•
PLL has not reached the initial lock (
deasserted)
• is deasserted and
pll_locked
deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
.
tx_digitalreset
Analog reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when is asserted.
reset
This signal follows
pll_powerdown
deasserted after
pll_locked
Status signal to indicate when the TX reset sequence is
complete. This signal is deasserted while the TX reset
is active. It is asserted a few clock cycles after the
deassertion of
tx_digitalreset
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of TX channels.
Digital reset for RX. The width of this signal depends
on the number of channels. This signal is asserted
when any of the following conditions is true:
® ®
Intel Arria 10 Transceiver PHY User Guide
signal is
logic
controller does
when
rx_ready
pll_locked
is
tx_manual
, which is
goes high.
. Some protocol
continued...
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