Intel Arria 10 User Manual page 54

Parameters
DFE adaptation mode
Number of fixed DFE
taps
Table 16. RX PMA Optional Ports
Parameters
Enable
rx_analog_reset_ack
port
Enable rx_pma_clkout
port
Enable
rx_pma_div_clkout
port
rx_pma_div_clkout
division factor
Enable
rx_pma_iqtxrx_clkout
port
Enable rx_pma_clkslip
port
(26)
This clock should not be used to clock the FPGA - transceiver interface. This clock may be used
as a reference clock to an external clock cleaner.
(27)
The default value is Disabled.
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Intel Arria 10 Transceiver PHY User Guide
54
Value
For manual mode, set the CTLE options through the Assignment
Editor, or modify the Quartus Settings File (.qsf), or write to the
reconfiguration registers using the Avalon Memory-Mapped
(Avalon-MM) interface.
Refer to
section in Arria 10 Transceiver Architecture chapter for more
details about CTLE architecture. Refer to
DFE
modes.
Adaptation enabled Specifies the operating mode for the Decision Feedback
Equalization (DFE) block in the RX PMA.
Manual, Disabled
The default value is Disabled.
For manual mode, you can set the DFE options through the
Assignment Editor, or by modifying the Quartus Settings File
(.qsf), or write to the reconfiguration registers using the Avalon-
MM interface.
Refer to the
section in the Arria 10 Transceiver PHY Architecture chapter for
more details about DFE. Refer to
page 456 for more details on supported adaptation modes.
3, 7 , 11 Specifies the number of fixed DFE taps. Select the number of
taps depending on the loss in your transmission channel and the
type of equalization required.
Value
On/Off
Enables the optional
should not be used for register mode data transfers.
On/Off
Enables the optional
the recovered parallel clock from the RX clock data recovery
(CDR).
On/Off
Enables the optional
deserializer generates this clock. Use this to drive core logic, to
drive the RX PCS-to-FPGA fabric interface, or both.
If you select a rx_pma_div_clkout division factor of 1 or 2, this
clock output is derived from the PMA parallel clock. If you select a
rx_pma_div_clkout division factor of 33, 40, or 66, this clock is
derived from the PMA serial clock. This clock is commonly used
when the interface to the RX FIFO runs at a different rate than the
PMA parallel clock frequency, such as 66:40 applications.
Disabled, 1, 2, 33, 40,
Selects the division factor for the
66
clock when enabled.
On/Off
Enables the optional
clock can be used to cascade the RX PMA output clock to the input
of a PLL.
On/Off
Enables the optional
edge on this signal causes the RX serializer to slip the serial data
by one clock cycle, or 2 unit intervals (UI).
2. Implementing Protocols in Arria 10 Transceivers
Description
Continuous Time Linear Equalization (CTLE)
on page 456 for more details on supported adaptation
Decision Feedback Equalization (DFE)
How to Enable CTLE and DFE
Description
rx_analog_reset_ack
rx_pma_clkout
(26)
rx_pma_div_clkout
rx_pma_div_clkout
(27)
rx_pma_iqtxrx_clkout
rx_pma_clkslip
UG-01143 | 2018.06.15
on page 452
How to Enable CTLE and
on page 454
on
output. This port
output clock. This port is
output clock. The
output
output clock. This
control input port. A rising
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