Intel Arria 10 User Manual page 170

Signal Name
calc_clk_1g
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
usr_seq_reset
rx_data_ready
Related Information
• Input Reference Clock Sources
• PLLs
2.6.4.5. Parameterizing the 1G/10GbE PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the
Backplane-KR or 1Gb/10Gb Ethernet variant. The 1Gb/10Gb Ethernet variant
(1G/10GbE) does not implement the link training and auto-negotiation functions.
Complete the following steps to parameterize the 1Gb/10Gb Ethernet PHY IP core in
the parameter editor:
1. Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
Refer to
2. Select 1Gb/10Gb Ethernet from the IP variant list located under Ethernet
Intel FPGA IP Core Type.
3. Use the parameter values in the tables in
10M/100M/1Gb Ethernet Parameters
on page 142, and
can select the BackPlane_wo_1588 option in the Presets tab on the right side
of the IP Parameter Editor. You can then modify the setting to meet your specific
requirements.
4. Click Generate HDL to generate the 1Gb/10Gb Ethernet IP core top-level HDL
file.
® ®
Intel Arria 10 Transceiver PHY User Guide
170
Direction
Input This is the clock for the GIGE PCS 1588 mode. To achieve high
accuracy for all speed modes, the recommended frequency for
calc_clk_1g
the same parts per million (ppm) as the 125 MHz
input. The random error without a rate match FIFO mode is:
•
•
•
Input Resets the analog TX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input Resets the digital TX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input Resets the analog RX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input Resets the digital RX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input Resets the sequencer. Initiates a PCS reconfiguration, and may
restart AN, LT or both if these modes are enabled. Synchronous to
mgmt_clk
Output When asserted, indicates that you can start to send the 10G data.
Synchronous to
on page 349
Select and Instantiate the PHY IP Core
PHY Analog Parameters
2. Implementing Protocols in Arria 10 Transceivers
Description
is 80 MHz. In addition, the 80 MHz clock should have
±1 ns at 1000 Mbps
± 5 ns at 100 Mbps
± 25 ns at 10 Mbps
.
.
.
.
.
.
xgmii_rx_clk
on page 372
on page 33.
10GBASE-R Parameters
on page 172 , Speed Detection Parameters
on page 173 as a starting point. Or, you
UG-01143 | 2018.06.15
pll_ref_clk_1g
on page 140,