Intel Arria 10 User Manual page 155

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Word Bit R/W
Addr
15 RW
16 RW
17 RW
0x4D0 18 RW
19 RW
21:20 RW
0x4D0 22 RW
Name
•
•
•
The default value is 101.
When set to 1, PMA values (VOD, Pre-tap, Post-tap) are not
disable Initialize
initialized upon entry into the
PMA on
happens when
max_wait_timeout
training_failure
testing. When set to 0, PMA values are initialized upon entry
into
802.3ap-2007 for more details. The default value is 0.
When set to 1, overrides the link partner's equalization
Ovride LP Coef
coefficients; software changes the update commands sent to
enable
the link partner TX equalizer coefficients. When set to 0, uses
the Link Training logic to determine the link partner
coefficients. Used with 0x4D1 bit-4 and 0x4D4 bits[7:0]. The
default value is 0.
When set to 1, overrides the local device equalization
Ovride Local RX Coef
coefficients generation protocol. When set, the software
enable
changes the local TX equalizer coefficients. When set to 0,
uses the update command received from the link partner to
determine local device coefficients. Used with 0x4D1 bit-8 and
0x4D4 bits[23:16]. The default value is 0.
Defines whether or not to skip adjustment of the link
VOD Training Enable
partner's VOD (main tap) during link training. The following
values are defined:
•
•
The default value is 0.
Defines whether or not Decision Feedback Equalization (DFE)
Bypass DFE
is enabled at the end of link training. The following values are
defined:
•
•
The default value for simulation is 1. The default value for
hardware is 0.
Defines the behavior of DFE taps at the end of link training
dfe_freeze_mode
•
•
•
•
The default value is 01.
Note: These bits are only effective when bit [19] is set to 0.
Defines whether or not CTLE/VGA adaptation is in adaptive or
adp_ctle_vga_mode
manual mode. The following values are defined:
•
•
The default value is 0 for hardware.
Description
101 = 32
110 = 64
111 = 128
Training_Failure
max_wait_timer_done
= true (reg 0xD2 bit 3). Used for UNH
state. Refer to Figure 72-5 of IEEE
Training_Failure
1 = Exercise VOD (main tap) adjustment during link
training
0 = Skip VOD (main tap) adjustment during link training
1 = Bypass continuous adaptive DFE at the end of link
training
0 = Enable continuous adaptive DFE at the end of link
training
00 = do not freeze any DFE taps
01 = Freeze all DFE taps
10 = reserved
11 = reserved
0 = CTLE sweep before start of TX-EQ during link training.
1 = manual CTLE mode. Link training algorithm sets fixed
CTLE value, as specified in bits [28:24]. The default value
is 1 for simulation. .
® ®
Intel Arria
state. This
, which sets
continued...
10 Transceiver PHY User Guide
155