Intel Arria 10 User Manual page 345

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Document
Version
• Changed the values for the PPM detector threshold parameter and removed the Decision feedback
equalization parameter in the "RX PMA Parameters" table.
• Changed the 10GBASE-R PHY grouping in the "10GBASE-R PHY as Part of the IEEE802.3-2008 Open
System Interconnection (OSI)" figure.
• Added that 10GBASE-R is compatible with the Altera 10-Gbps Ethernet MAC Intel FPGA IPCore
Function in the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
section.
• Added the "Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2" figure.
• Changed steps 1 and 4 in the How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers section to match the GUI.
• Specified the target BER of 10
• Removed the "Top Level Modules of the 1G/10GbE PHY Intel FPGA IP Core Function" figure.
• Removed the 10GBASE-KR PHY with 1588 variant from the "10GBASE-KR PHY Performance and
Resource Utilization" table. This is not supported.
• Replaced the "10GBASE-KR PHY IP Block Diagram" figure.
• Added the Auto Negotiation, IEEE 802.3 Clause 73 section.
• Substantially rewrote the Link Training (LT), IEEE 802.3 Clause 72 section.
• Removed the "TX Equalization for Link Partners" figure.
• Removed the "TX Equalization in Daisy Chain Mode" figure. Daisy chain is not supported.
• Removed the Auto Negotiation section.
• Replaced the "Reconfiguration Block Details" figure.
• Removed the Initial Datapath, Enable internal PCS reconfiguration logic, and Enable IEEE
1588 Precision time Protocol parameters from the "General Options Parameters" table.
• Added the Reference clock frequency, Enable additional control and status pins, Include
FEC sublayer, Set FEC_ability bit on power up and reset, and Set FEC_Enable bit on power
up and reset parameters to the "General Options Parameters" table.
• Removed the 10GBASE-R Parameters section.
• Removed the 10M/100M/1Gb Ethernet Parameters section.
• Removed the Speed Detection Parameters section.
• Substantially changed the "Auto Negotiation and Link Training Settings" table, adding the
AN_PAUSE Pause Ability, CAPABLE_FEC ENABLE_FEC (request), AN_TECH Technology
Ability, AN_SELECTOR Selector Field, and Width of the Training Wait Counter parameters.
• Updated all parameter names, values, and descriptions in the "Optional Parameters" table.
• Updated the signals in the "10GBASE-KR Top-Level Signals" figure.
•
Removed the
"1G" from all descriptions in the "Clock and Reset Signals" table.
• Removed references to GMII and MII interfaces from the Data Interfaces section.
• Removed GMII and MII signals from the "XGMII Signals" table.
• Updated the list of signals in the "Control and Status Signals" table.
• Removed the Daisy-Chain Interface Signals section.
• Removed the Embedded Processor Interface Signals section.
• Updated the list of signals in the "Dynamic Reconfiguration Interface Signals" table.
• Added new registers and updated descriptions of existing registers in the "10GBASE-KR Register
Definitions" table.
• Updated the 0x482 registers in the "PCS Registers" table.
• Updated and removed some addresses in the "PMA Registers" table.
• Added the Speed Change Summary section.
• Removed the 10GBASE-KR, Backplane, FEC, GMII PCS Registers section.
• Removed the 1588 Delay Requirement section.
• Removed the Channel Placement Guidelines section.
• Removed the introductory paragraph from the Design Example section.
• Removed the 1588 FIFO block from the "Top Level Modules of the 1G/10GbE PHY Intel FPGA IP
Core Function" figure.
• Updated all values for ALMs, ALUTs, Registers, and M20K in the "1G/10GbE PHY Performance and
Resource Utilization" table.
• Updated the blocks in the "Reconfiguration Block Details" figure.
-12
in the 10GBASE-KR PHY IP Core section.
and
rx_serial_clk_1g tx_serial_clk_1g
Changes
signals, and removed all references to
® ®
Intel Arria 10 Transceiver PHY User Guide
continued...
345