Intel Arria 10 User Manual page 184

Word Bit R/W
Addr
2 RO
3 RO
4 RO
5 RO
6 RO
7 RO
8 RO
0x4C2 9 RO
17:12 RO
0x4C3 15:0 RW
21:16 RW
25:24 RW
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Intel Arria 10 Transceiver PHY User Guide
184
Name
When asserted, AN has completed. When 0, AN is in progress. For
AN Complete
more information, refer to bit 7.1.5 in Clause 73.8 of IEEE
802.3ap-2007.
When set to 1, fault information has been sent to the link partner.
AN ADV Remote Fault
When 0, a fault has not occurred. The current value clears when
the register is read. Remote Fault (RF) is encoded in bit D13 of
the base Link Codeword. For more information, refer to Clause
73.6.7 of and bit 7.16.13 of IEEE 802.3ap-2007.
When set to 1, the AN state machine is in the idle state. Incoming
AN RX SM Idle
data is not Clause 73 compatible. When 0, the AN is in progress.
When set to 1, the transceiver PHY is able to perform AN. When
AN Ability
set to 0, the transceiver PHY is not able to perform AN. If your
variant includes AN, this bit is tied to 1. For more information,
refer to bits 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
When set to 1, link is up. When 0, the link is down. The current
AN Status
value clears when the register is read. For more information, refer
to bit 7.1.2 of Clause 45 of IEEE 802.3ap-2007.
When set to 1, the link partner is able to perform AN. When 0,
LP AN Ability
the link partner is not able to perform AN. For more information,
refer to bit 7.1.0 of Clause 45 of IEEE 802.3ap-2007.
When set to 1, the PHY is negotiated to perform FEC. When set to
FEC negotiated –
0, the PHY is not negotiated to perform FEC.
enable FEC from SEQ
When set to 1, a sequencer AN failure has been detected. When
Seq AN Failure
set to 0, an AN failure has not been detected.
Provides a one-hot encoding of
KR AN Link
link status for the supported link as described in Clause 73.10.1.
Ready[5:0]
The following encodings are defined:
•
•
•
•
•
•
The AN TX state machine uses these bits if the AN base pages ctrl
User base page low
bit is set. The following bits are defined:
•
•
•
•
•
•
The auto generation TX state machine generates the PRBS bit 49.
Override AN_TECH
•
AN_TECH[5:0]
•
You must set 0xC0 bit-5 for this to take effect .
Override AN_FEC
•
AN_FEC[1:0]
•
You must set 0xC0 bit-5 for this to take effect.
2. Implementing Protocols in Arria 10 Transceivers
Description
an_receive_idle = true
6'b000000: 1000BASE-KX
6'b000001: 10GBASE-KX4
6'b000100: 10GBASE-KR
6'b001000: 40GBASE-KR4
6'b010000: 40GBASE-CR4
6'b100000: 100GBASE-CR10
[15]: Next page bit
[14]: ACK, controlled by the SM
[13]: Remote Fault bit
[12:10]: Pause bits
[9:5]: Echoed nonce, set by the state machine
[4:0]: Selector
value to override. The following bits are defined:
Bit-16 = = 1000BASE-KX
AN_TECH[0]
Bit-18 = = 10GBASE-KR
AN_TECH[2]
value to override. The following bits are defined:
Bit-24 = = Capability
AN_FEC [0]
Bit-25 = = Request
AN_FEC [1]
UG-01143 | 2018.06.15
and
continued...