Intel Arria 10 User Manual page 318

Number of invalid data words to lose sync
Number of valid data words to decrement error count
Enable fast sync status reporting for deterministic latency SM
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel port
Enable rx_bitslip port
Enable TX bit reversal
Enable TX byte reversal
Enable TX polarity inversion
Enable tx_polinv port
Enable RX bit reversal
Enable rx_std_bitrev_ena port
Enable RX byte reversal
Enable rx_std_byterev_ena port
Enable RX polarity inversion
Enable rx_polinv port
Enable rx_std_signaldetect port
Enable PCIe dynamic datarate switch ports
Enable PCIe pipe_hclk_in and pipe_hclk_out ports
Enable PCIe Gen 3 analog control ports
Enable PCIe electrical idle control and status ports
Enable PCIe pipe_rx_polarity port
Table 221. Dynamic Reconfiguration Parameters
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master Endpoint
Table 222. Generation Options Parameters
Generate parameter documentation file
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
® ®
Intel Arria 10 Transceiver PHY User Guide
318
Parameter
Parameter
Parameter
2. Implementing Protocols in Arria 10 Transceivers
Range
0-63
0-255
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
On/Off
Range
On/Off
On/Off
On/Off
Range
On/Off
on page 45
UG-01143 | 2018.06.15
Off
Off
Off
Off
Off