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2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
2.6.4.6.1. Clock and Reset Interfaces
Table 135.
Clock and Reset Signals
Signal Name
tx_serial_clk_10g
tx_serial_clk_1g
rx_cdr_ref_clk_10g
rx_cdr_ref_clk_1g
tx_pma_clkout
rx_pma_clkout
tx_clkout
rx_clkout
tx_pma_div_clkout
rx_pma_div_clkout
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
usr_seq_reset
Related Information
•
Input Reference Clock Sources
•
PLLs
Direction
Input
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The
frequency of this clock is 5.15625 GHz.
Input
High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock
is not required if GbE is not used. The frequency of this clock is 625
MHz.
Input
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
Input
1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock
is only required if 1G is enabled.
Output
Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
Output
Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
Output
XGMII/GMII TX clock for the TX parallel data source interface. This
clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with
FEC enabled.
Output
XGMII RX clock for the RX parallel data source interface. This clock
frequency is 257.81 in 10G mode, and 161.13 MHz with FEC
enabled.
Output
The divided 33 clock from the TX serializer. You can use this clock for
the for
MHz for 10G. The frequencies are the same whether or not you
enable FEC.
Output
The divided 33 clock from CDR recovered clock. The frequency is
156.25 MHz for 10G. The frequencies are the same whether or not
you enable FEC. This clock is not used for clocking the 10G RX
datapath.
Input
Resets the analog TX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input
Resets the digital TX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input
Resets the analog RX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input
Resets the digital RX portion of the transceiver PHY. Synchronous to
mgmt_clk
Input
Resets the sequencer. Initiates a PCS reconfiguration, and may
restart AN, LT or both if these modes are enabled. Synchronous to
mgmt_clk
on page 349
Description
or
xgmii_tx_clk
xgmii_rx_clk
.
.
.
.
.
on page 372
®
Intel
Arria
. The frequency is 156.25
®
10 Transceiver PHY User Guide
175
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