Intel Arria 10 User Manual page 310

Figure 151. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6
tx_parallel_data[19:0]
tx_parallel_data[9:0]
rx_parallel_data[19:10]
rx_parallel_data[9:0]
rx_std_rmfifo_empty
2.9.2.9. 8B/10B Encoder and Decoder
To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX
8B/10B Encoder and Enable RX 8B/10B Decoder options on the Standard PCS
tab in the IP Editor. Platform Designer (Standard) allows implementing the 8B/10B
decoder in RX-only mode.
The following ports are added:
•
tx_datak
•
rx_datak
•
rx_runningdisp
•
rx_disperr
•
rx_errdetect
rx_datak
data word. The incoming 8-bit data (
(
tx_datak
encoder takes the 10-bit data from the RD- column. Next, the encoder chooses the
10-bit data from the RD+ column to maintain neutral disparity. The running disparity
is shown by
2.9.2.10. 8B/10B TX Disparity Control
The Disparity Control feature controls the running disparity of the output from the
8B/10B Decoder.
To enable TX Disparity Control, select the Enable TX 8B/10B Disparity Control
option. The following ports are added:
•
tx_forcedisp
be forced or not
•
tx_dispval
being forced
When the number of data channels is more than 1,
are shown as buses in which each bit corresponds to one channel.
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Intel Arria 10 Transceiver PHY User Guide
310
D2
D1
D2
D1
and indicate whether the parallel data is a control word or a
tx_datak
) are converted into a 10-bit data. After a power on reset, the 8B/10B
.
rx_runningdisp
—a control signal that indicates whether a disparity value has to
—a signal that indicates the value of the running disparity that is
2. Implementing Protocols in Arria 10 Transceivers
D4 D6 D8
D3 D5 D7
D4 D6 /K30.7/
D3 D5 /K30.7/
) and the control identifier
tx_parallel_data
tx_forcedisp
UG-01143 | 2018.06.15
D10 D12
D11
D9
D8 D10
D9
D7
and
tx_dispval