Intel Arria 10 User Manual page 365

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Table 237. Clock Switchover (between Dynamic Reconfiguration and General Options)
Clock Switchover Parameter
Create a second input clock
pllrefclk1
Second Reference Clock Frequency
Switchover Mode
Switchover Delays
Create an active_clk signal to
indicate the input clock in use
Create a clkbad signal for each of
the input clocks
Table 238. fPLL - Generation Options
Parameter
Generates parameter
documentation file
Table 239. fPLL IP Core Ports
Port
pll_powerdown
pll_refclk0
pll_refclk1
Range
On/Off
User Defined
Automatic Switchover
Manual Switchover
Automatic Switchover with Manual
Override
0 to 7
On/Off
On/Off
Direction
On/Off Generates a .csv file that contains descriptions of all the
fPLL parameters and values.
Direction Clock Domain
input Asynchronous
input N/A
input N/A
Description
Turn on this parameter to have a
backup clock attached to your fPLL that
can switch with your original reference
clock
Specifies the second reference clock
frequency for fPLL
Specifies how Input frequency
switchover is handled. Automatic
Switchover uses built in circuitry to
detect if one of your input clocks has
stopped toggling and switch to the
other.
Manual Switchover creates an
signal which can be used
EXTSWITCH
to manually switch the clock by
asserting high for at least 3 cycles.
Automatic Switchover with Manual
Override acts as Automatic Switchover
until the goes high, in
EXTSWITCH
which case it switches and ignores any
automatic switches as long as
stays high.
EXTSWITCH
Adds a specific amount of cycle delay
to the Switchover Process.
This parameter creates an output that
indicates which input clock is currently
in use by the PLL. Low indicates
, High indicates refclk1.
refclk
This parameter creates two
outputs, one for each input clock. Low
indicates the is working, High
CLK
indicates the is not working.
CLK
Description
Description
Resets the PLL when asserted high.
Needs to be connected to a
dynamically controlled signal (the
Transceiver PHY Reset Controller
pll_powerdown output if using this
Intel FPGA IP).
Reference clock input port 0.
There are five reference clock input
ports. The number of reference clock
ports available depends on the
Number of PLL reference clocks
parameter.
Reference clock input port 1.
continued...
® ®
Intel Arria 10 Transceiver PHY User Guide
clkbad
365