Intel Arria 10 User Manual page 265

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Port
pll_locked
pll_pcie_clk
Pll_cal_busy
Mcgb_rst
mcgb_aux_clk0
tx_bonding_clocks[6n-1:0]
pcie_sw[1:0]
pcie_sw_done[1:0]
Related Information
Using the Arria 10 Transceiver Native PHY IP Core
Direction Clock Domain
Output Asynchronous
Output N/A
Output Asynchronous
Input Asynchronous
Input N/A
Output N/A
]
Input Asynchronous
Output Asynchronous
Description
Active high status signal which indicates if PLL is locked.
This is the hclk required for PIPE interface.
For Gen1x1, x2, x4, x8 use this port to drive the
the PIPE interface.
For Gen2x1, x2, x4, x8 use this port to drive the
the PIPE interface.
For Gen3x1, x2, x4, x8, use the
(configured as Gen1/Gen2) as the hclk for the PIPE
interface.
Status signal which is asserted high when PLL calibration is
in progress.
If this port is not enabled in Transceiver PHY Reset
Controller, then perform logical OR with this signal and the
output signal from Native PHY to input the
tx_cal_busy
on the reset controller IP.
tx_cal_busy
Master CGB reset control.
Used for Gen3 to switch between fPLL/ATX PLL during link
speed negotiation. For gen3x2, x4, x8 use the
input port on the ATX PLL.
mcgb_aux_clk
Optional 6-bit bus which carries the low speed parallel
clock outputs from the Master CGB. It is used for channel
bonding, and represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2, x4, x8 connect the output from this port to
the input on Native PHY.
tx_bonding_clocks
For Gen2x1, this port is disabled.
For Gen2x2, x4, x8 connect the output from this port to
the input on Native PHY.
tx_bonding_clocks
For Gen3x1, this port is disabled.
For Gen3x2, x4, x8, use the
tx_bonding_clocks
from the ATX PLL to connect to the
input of the Native PHY.
2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A
For Gen 2x2, x4, x8 connect the
Native PHY to this port.
For Gen3x2, x4, x8 connect the
Native PHY to this port.
For Gen3x2, x4, x8, this port is not used. You must use the
from Native PHY to drive the
pipe_sw
on the ATX PLL.
2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2, x4, x8 connect the
from ATX PLL to the
pipe_sw_done
For Gen3x2, x4, x8 connect the
from ATX PLL to the
pipe_sw_done
on page 45
® ®
Intel Arria
for
hclk
for
hclk
from fPLL
pll_pcie_clk
output
tx_bonding_clocks
output from
pipe_sw
output from the
pipe_sw
input port
pcie_sw
output
pcie_sw_done
input of Native PHY .
output
pcie_sw_done
input of Native PHY.
10 Transceiver PHY User Guide
265