Intel Arria 10 User Manual page 195

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Table 148. 1G Data Mode
Addr Bit
0x4A8 0 RW
1 RW
2 RW
3 RW
4 RW
0x4A9 0 R
1 R
2 R
3 R
4 R
5 R
6 R
Table 149. PMA Registers
Address Bit
0x444 1
2
3
0x461 0
0x464 0
0x465 0
0x466 0
0x467 0
R/W Name
tx_invpolarity
rx_invpolarity
rx_bitreversal_enable
rx_bytereversal_enable
force_electrical_idle
rx_syncstatus
rx_patterndetect
rx_rlv
rx_rmfifodatainserted
rx_rmfifodatadeleted
rx_disperr
rx_errdetect
R/W Name
RW
reset_tx_digital
RW
reset_rx_analog
RW
reset_rx_digital
RW
phy_serial_loopback
RW
pma_rx_set_locktoda
ta
RW
pma_rx_set_locktore
f
RO
pma_rx_is_lockedtod
ata
RO
pma_rx_is_lockedtor
ef
Description
When set, the TX interface inverts the polarity of
the TX data to the 8B/10B encoder.
When set, the RX channels inverts the polarity of
the received data to the 8B/10B decoder.
When set, enables bit reversal on the RX interface
to the word aligner.
When set, enables byte reversal on the RX interface
to the byte deserializer.
When set, forces the TX outputs to electrical idle.
When set, the word aligner is synchronized.
GbE word aligner detected comma.
Run length violation.
Rate match FIFO inserted code group.
Rate match FIFO deleted code group.
RX 8B10B disparity error.
RX 8B10B error detected.
Description
Writing a 1 asserts the internal TX digital reset signal. You
must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX analog reset signal to be
asserted. You must write a 0 to clear the reset condition.
Writing a 1 causes the internal RX digital reset signal to be
asserted. You must write a 0 to clear the reset condition.
Writing a 1 puts the channel in serial loopback mode.
When set, programs the RX clock data recovery (CDR) PLL
to lock to the incoming data.
When set, programs the RX CDR PLL to lock to the reference
clock.
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode.
When asserted, indicates that the RX CDR PLL is locked to
the reference clock.
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Intel Arria 10 Transceiver PHY User Guide
195