Intel Arria 10 User Manual page 390

The steps below explain the x6/xN bonding process:
1. The ATX PLL or the fPLL generates a high speed serial clock.
2. The PLL drives the high speed serial clock to the master CGB via the x1 clock
network.
3. The master CGB drives the high speed serial and the low speed parallel clock into
the x6 clock network.
4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels
within the same transceiver bank. The local CGB in each transceiver channel is
bypassed.
5. To drive the channels in adjacent transceiver banks, the x6 clock network drives
the xN clock network. The xN clock network feeds the TX clock mutiplexer for the
transceiver channels in these adjacent transceiver banks.
x6/xN Bonding Disadvantages
x6/xN Bonding has the following disadvantages:
• The maximum data rate is restricted based on the transceiver supply voltage.
Refer to Arria 10 Device Data Sheet.
• The maximum channel span is limited to two transceiver banks above and below
the bank containing the transmit PLL. Thus, the maximum span of 30 channels is
supported.
Related Information
• xN Clock Lines
• Arria 10 Device Datasheet
3.9.1.2. PLL Feedback Compensation Bonding
In PLL feedback compensation bonding, channels are divided into bonded groups
based on physical location with a three-channel or six-channel transceiver bank. All
channels within the same six-channel transceiver bank are assigned to the same
bonded group.
In PLL feedback compensation bonding, each bonded group is driven by its own set of
high-speed serial and low-speed parallel clocks. Each bonded group has its own PLL
and master CGB. To maintain the same phase relationship, the PLL and master CGB
for different groups share the same reference clocks.
The steps below explain the PLL feedback compensation bonding process:
1. The same input reference clock drives the local PLL in each three-channel or six-
channel transceiver bank.
2. The local PLL for the bonding group drives the master CGB.
3. The master CGB feeds the x6 clock lines. The master CGB drives the transceiver
channels in the bonding group via the x6 clock network.
4. The parallel output of the master CGB is the feedback input to the PLL.
5. In this mode, all channels are phase aligned to the same input reference clock.
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Intel Arria 10 Transceiver PHY User Guide
390
on page 379
3. PLLs and Clock Networks
UG-01143 | 2018.06.15