Intel Arria 10 User Manual page 4

3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs.................. 349
3.1.2. ATX PLL................................................................................................ 350
3.1.3. fPLL......................................................................................................359
3.1.4. CMU PLL............................................................................................... 368
3.2. Input Reference Clock Sources............................................................................372
3.2.1. Dedicated Reference Clock Pins............................................................... 374
3.2.2. Receiver Input Pins.................................................................................374
3.2.3. PLL Cascading as an Input Reference Clock Source..................................... 375
3.2.4. Reference Clock Network.........................................................................375
3.2.5. Global Clock or Core Clock as an Input Reference Clock............................... 375
3.3. Transmitter Clock Network..................................................................................375
3.3.1. x1 Clock Lines....................................................................................... 376
3.3.2. x6 Clock Lines....................................................................................... 377
3.3.3. xN Clock Lines....................................................................................... 379
3.3.4. GT Clock Lines....................................................................................... 381
3.4. Clock Generation Block....................................................................................... 383
3.5. FPGA Fabric-Transceiver Interface Clocking............................................................ 384
3.6. Transmitter Data Path Interface Clocking............................................................... 386
3.7. Receiver Data Path Interface Clocking................................................................... 387
3.8. Unused/Idle Clock Line Requirements................................................................... 389
3.9. Channel Bonding................................................................................................389
3.9.1. PMA Bonding......................................................................................... 389
3.9.2. PMA and PCS Bonding.............................................................................391
3.9.3. Selecting Channel Bonding Schemes......................................................... 392
3.9.4. Skew Calculations.................................................................................. 393
3.10. PLL Feedback and Cascading Clock Network......................................................... 393
3.11. Using PLLs and Clock Networks.......................................................................... 398
3.11.1. Non-bonded Configurations....................................................................398
3.11.2. Bonded Configurations.......................................................................... 403
3.11.3. Implementing PLL Cascading..................................................................408
3.11.4. Mix and Match Example.........................................................................409
3.11.5. Timing Closure Recommendations...........................................................413
3.12. PLLs and Clock Networks Revision History............................................................414
4. Resetting Transceiver Channels.................................................................................. 416
4.1. When Is Reset Required? ................................................................................... 416
4.2. Transceiver PHY Implementation.......................................................................... 417
4.3. How Do I Reset?................................................................................................ 418
4.3.1. Model 1: Default Model........................................................................... 418
4.3.2. Model 2: Acknowledgment Model..............................................................427
4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals....................... 432
4.4. Using the Transceiver PHY Reset Controller............................................................ 433
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP............................... 435
4.4.2. Transceiver PHY Reset Controller Parameters............................................. 435
4.4.3. Transceiver PHY Reset Controller Interfaces............................................... 437
4.4.4. Transceiver PHY Reset Controller Resource Utilization.................................. 441
4.5. Using a User-Coded Reset Controller.....................................................................441
4.5.1. User-Coded Reset Controller Signals......................................................... 441
4.6. Combining Status or PLL Lock Signals .................................................................. 442
4.7. Timing Constraints for Bonded PCS and PMA Channels............................................ 443
4.8. Resetting Transceiver Channels Revision History..................................................... 445
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Intel Arria 10 Transceiver PHY User Guide
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