Intel Arria 10 User Manual page 459

5. Arria 10 Transceiver PHY Architecture
UG-01143 | 2018.06.15
5.1.2.2.2. Lock-to-Data Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the
incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data
at the receiver input. Depending on the phase difference between the incoming data
and the CDR output clock, the PD controls the CDR charge pump that tunes the VCO.
Note:
The PFD is inactive in LTD mode. The
randomly and is not significant in LTD mode.
After switching to LTD mode, the
The actual lock time depends on the transition density of the incoming data and the
parts per million (ppm) difference between the receiver input reference clock and the
upstream transmitter reference clock. The
the CDR sees valid data; therefore, you should hold receiver PCS logic in reset
(
rx_digitalreset
continuously asserted.
5.1.2.2.3. CDR Lock Modes
You can configure the CDR in either automatic lock mode or manual lock mode. By
default, the Quartus Prime software configures the CDR in automatic lock mode.
Automatic Lock Mode
In automatic lock mode, the CDR initially locks to the input reference clock (LTR
mode). After the CDR locks to the input reference clock, the CDR locks to the
incoming serial data (LTD mode) when the following conditions are met:
• The signal threshold detection circuitry indicates the presence of valid signal levels
at the receiver input buffer when
• The CDR output clock is within the configured ppm frequency threshold setting
with respect to the input reference clock (frequency locked).
• The CDR output clock and the input reference clock are phase matched within
approximately 0.08 unit interval (UI) (phase locked).
If the CDR does not stay locked to data because of frequency drift or severe amplitude
attenuation, the CDR switches back to LTR mode.
Manual Lock Mode
The PPM detector and phase relationship detector reaction times can be too long for
some applications that require faster CDR lock time. You can manually control the CDR
to reduce its lock time using two optional input ports (
rx_set_locktodata
Table 253. Relationship Between Optional Input Ports and the CDR Lock Mode
rx_set_locktoref
0
1
X
rx_is_lockedtoref
rx_is_lockedtodata
rx_is_lockedtodata
) for a minimum of 4 µs after
rx_std_signaldetect
).
rx_set_locktodata
0
0
1
status signal toggles
status signal is asserted.
signal toggles until
rx_is_lockedtodata
is enabled.
rx_set_locktoref
CDR Lock Mode
Automatic
Manual-RX CDR LTR
Manual-RX CDR LTD
® ®
Intel Arria 10 Transceiver PHY User Guide
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