Intel Arria 10 User Manual page 243

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 104. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode
fPLL1
ATX PLL1
fPLL0
ATX PLL0
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x1 mode.
2. Gen1/Gen2 modes use the fPLL only.
3. Gen3 mode uses the ATX PLL only.
4. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
5. Select the number of TX PLLs (2) in the Native PHY IP core wizard.
X1 Network
Master 4
CGB1
4
Master
CGB0
Ch 5
6
CGB
CDR
Ch 4
6
CGB
CDR
Ch 3
6
CGB
CDR
Ch 2
6
CGB
CDR
Ch 1
6
CGB
CDR
Ch 0
6
CGB
CDR
® ®
Intel Arria 10 Transceiver PHY User Guide
243