Intel Arria 10 User Manual page 235

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Figure 93. Rate Match Insertion
The figure below shows an example of rate match insertion in the case where two SKP symbols must be
inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
rmfifo_input_data
rx_parallel_data
pipe_rx_status[2:0]
Figure 94. Rate Match FIFO Full
The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and
drives
pipe_rx_status[2:0]
the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data byte
D4.
tx_parallel_data
rx_parallel_data
pipe_rx_status[2:0]
Figure 95. Rate Match FIFO Empty
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become
empty and drives
below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after
reading out data byte D3.
tx_parallel_data
rx_parallel_data
pipe_rx_status[2:0]
PIPE 0 ppm
The PIPE mode also has a "0 ppm" configuration option that can be used in
synchronous systems. The Rate Match FIFO Block is not expected to do any clock
compensation in this configuration, but latency is minimized.
2.7.2.1.8. PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for
Gen1, Gen2, and Gen3 data rates. The received serial data passes through the
receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is
then looped back to the transmitter serializer and transmitted out through the
transmitter buffer. The received data is also available to the FPGA fabric through the
rx_parallel_data
Arria 10 devices provide an input signal
this loopback mode.
Note: This is the only loopback option supported in PIPE configurations.
First SKP Ordered Set
K28.5 K28.0 Dx.y K28.5
K28.5 K28.0 K28.0 Dx.y
3'b001 xxx xxx xxx
= 3'b101 synchronous to the subsequent data byte. The figure below shows
D1 D2 D3
D1 D2 D3
xxx xxx xxx
= 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure
pipe_rx_status[2:0]
D1 D2
D1 D2
xxx xxx
port. This loopback mode is based on PCIe specification 2.0.
Second SKP Ordered Set
K28.0 K28.0 K28.0
K28.5 K28.0 K28.0
3'b001 xxx xxx
SKP Symbol Inserted
D4 D5 D6 D7
D7
D4 D6 D8
xxx 3'b101 xxx xxx
D3 D4
D3 /K.30.7/
xxx 3'b110
pipe_tx_detectrx_loopback
®
Intel Arria
K28.0
K28.0 K28.0 K28.0
xxx xxx xxx
D8
xx xx xx
xxx
D5 D6
D5
D4
xxx
xxx
to enable
®
10 Transceiver PHY User Guide
235