Intel Arria 10 User Manual page 147

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Signal Name
led_panel_link
rx_block_lock
rx_hi_ber
rx_is_lockedtodat
a
tx_cal_busy
rx_cal_busy
tx_pcfifo_error_1
g
rx_pcfifo_error_1
g
lcl_rf
rx_clkslip
rx_data_ready
rx_latency_adj_10
g[15:0]
Direction Clock Domain
Output Synchronous to
mgmt_clk
Output Synchronous to
rx_clkout
Output Synchronous to
rx_clkout
Output Asynchronous signal
Output Synchronous to
mgmt_clk
Output Synchronous to
mgmt_clk
Output N/A
Output N/A
Input Synchronous to
xgmii_tx_clk
Input Asynchronous signal
Output Synchronous to
xgmii_rx_clk
Output Synchronous to
xgmii_rx_clk
Description
When asserted, this signal indicates the following
behavior:
Mode
1000 Base-X without Auto-
negotiation
SGMII mode without Auto-
negotiation
1000 Base-X with Auto-
negotiation
SGMII mode with MAC
mode Auto-negotiation
Asserted to indicate that the block synchronizer has
established synchronization.
Asserted by the BER monitor block to indicate a Sync
Header high bit error rate greater than 10
When asserted, indicates the RX channel is locked to input
data.
When asserted, indicates that the TX channel is being
calibrated.
When asserted, indicates that the RX channel is being
calibrated.
When asserted, indicates that the standard PCS TX phase
compensation FIFO is either full or empty.
When asserted, indicates that the Standard PCS RX phase
compensation FIFO is either full or empty.
When asserted, indicates a Remote Fault (RF).The MAC
sends this fault signal to its link partner. Bit D13 of the
Auto Negotiation Advanced Remote Fault
(0xC2) records this error.
When asserted, the deserializer either skips one serial bit
or pauses the serial clock for one cycle to achieve word
alignment. As a result, the period of the parallel clock
could be extended by 1 unit interval (UI) during the clock
slip operation.This is an optional control input signal.
When asserted, indicates that the MAC can begin sending
data to the PHY.
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the RX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
® ®
Intel Arria 10 Transceiver PHY User Guide
Behavior
When asserted, indicates
successful link
synchronization.
When asserted, indicates
successful link
synchronization.
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
-4
.
register
continued...
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