Intel Arria 10 User Manual page 538

Table 282. Avalon Interface Parameters
The following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY
and TX PLL parameter editors.
Note:
Parameter
Enable dynamic reconfiguration
Share reconfiguration interface
Enable Altera Debug Master
Endpoint
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
Enable capability registers
Set user-defined IP identifier
Enable control and status
registers
Enable PRBS soft accumulators
Configuration file prefix
Generate SystemVerilog package
file
Generate C header file
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Intel Arria 10 Transceiver PHY User Guide
538
6. Reconfiguration Interface and Dynamic Reconfiguration
The Native PHY and the PLL IP Parameter Editors give an error or warning message if any of
the parameter selections violate the legality checks.
Value
On / Off Available in Native PHY and TX PLL IP parameter editors. Enables
the reconfiguration interface. Off by default. The reconfiguration
interface is exposed when this option is enabled.
On / Off Available in Native PHY IP parameter editor only. Enables you to
use a single reconfiguration interface to control all channels. Off
by default. If enabled, the uppermost bits of
identifies the active channel. The lower 10 bits specify the
reconfiguration address. Binary encoding is used to identify the
active channel (available only for Transceiver Native PHY). Enable
this option if the Native PHY is configured with more than one
channel.
On / Off Available in Native PHY and TX PLL IP parameter editors. When
enabled, the Altera Debug Master Endpoint (ADME) is instantiated
and has access to the Avalon-MM interface of the Native PHY. You
can access certain test and debug functions using System Console
with the ADME. Refer to the Embedded Debug Features section
for more details about ADME.
On / Off
When enabled,
status of AVMM arbitration with PreSICE. The AVMM arbitration
status is reflected in a soft status register bit. This feature
requires that the Enable control and status registers feature
under Optional Reconfiguration Logic be enabled. Refer to
Arbitration for more details on this feature. Refer to the
Calibration chapter for more details about calibration.
On / Off Available in Native PHY and TX PLL IP parameter editors. Enables
capability registers. These registers provide high-level information
about the transceiver channel's /PLL's configuration.
User-specified Available in Native PHY and TX PLL IP parameter editors. Sets a
user-defined numeric identifier that can be read from the
user_identifier
enabled.
On / Off Available in Native PHY and TX PLL IP parameter editors. Enables
soft registers for reading status signals and writing control signals
on the PHY /PLL interface through the ADME or reconfiguration
interface.
On / Off Available in Native PHY IP parameter editor only. Enables soft
logic to perform PRBS bit and error accumulation when using the
hard PRBS generator and checker.
User-specified Available in Native PHY and TX PLL IP parameter editors. Specifies
the file prefix used for generating configuration files. Use a unique
prefix for configuration files for each variant of the Native PHY
and PLL.
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a SystemVerilog package file that contains the current
configuration data values for all reconfiguration addresses.
Disabled by default.
On / Off Available in Native PHY and TX PLL IP parameter editors. Creates
a C header file that contains the current configuration data values
for all reconfiguration addresses. Disabled by default.
UG-01143 | 2018.06.15
Description
reconfig_address
do not indicate the
reconfig_waitrequest
offset when the capability registers are
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