Intel Arria 10 User Manual page 145

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Signal Name
Output
xgmii_rx_dc[71:0
]
Input
xgmii_rx_clk
2.6.3.5.3. XGMII Mapping to Standard SDR XGMII Data
Table 116. TX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name
xgmii_tx_dc[7:0]
xgmii_tx_dc[8]
xgmii_tx_dc[16:9]
xgmii_tx_dc[17]
xgmii_tx_dc[25:18]
xgmii_tx_dc[26]
xgmii_tx_dc[34:27]
xgmii_tx_dc[35]
xgmii_tx_dc[43:36]
xgmii_tx_dc[44]
xgmii_tx_dc[52:45]
xgmii_tx_dc[53]
xgmii_tx_dc[61:54]
xgmii_tx_dc[62]
xgmii_tx_dc[70:63]
xgmii_tx_dc[71]
Direction Clock Domain
Synchronous to
xgmii_rx_clk
Clock signal
SDR XGMII Signal Name
xgmii_sdr_data[7:0]
xgmii_sdr_ctrl[0]
xgmii_sdr_data[15:8]
xgmii_sdr_ctrl[1]
xgmii_sdr_data[23:16]
xgmii_sdr_ctrl[2]
xgmii_sdr_data[31:24]
xgmii_sdr_ctrl[3]
xgmii_sdr_data[39:32]
xgmii_sdr_ctrl[4]
xgmii_sdr_data[47:40]
xgmii_sdr_ctrl[5]
xgmii_sdr_data[55:48]
xgmii_sdr_ctrl[6]
xgmii_sdr_data[63:56]
xgmii_sdr_ctrl[7]
Description
recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz
for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
RX XGMII data and control for 8 lanes. Each lane consists of 8
bits of data and 1 bit of control.
Clock for SDR XGMII RX interface to the MAC. This clock can
be connected to the
tx_div_clkout
recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz
for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
Lane 0 data
Lane 0 control
Lane 1 data
Lane 1 control
Lane 2 data
Lane 2 control
Lane 3 data
Lane 3 control
Lane 4 data
Lane 4 control
Lane 5 data
Lane 5 control
Lane 6 data
Lane 6 control
Lane 7 data
Lane 7 control
®
Intel Arria
; however, Intel
Description
®
10 Transceiver PHY User Guide
145