Intel Arria 10 User Manual page 282

To avoid transmission interference in time division multiplexed systems, every radio in
a cell network requires accurate delay estimates with minimal delay uncertainty. Lower
delay uncertainty is always desired for increased spectrum efficiency and bandwidth.
The Arria 10 devices are designed with features to minimize the delay uncertainty for
both RECs and REs.
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI
The deterministic latency state machine in the word aligner reduces the known delay
variation from the word alignment process. It automatically synchronizes and aligns
the word boundary by slipping one half of a serial clock cycle (1UI) in the deserializer.
Incoming data to the word aligner is aligned to the boundary of the word alignment
pattern (K28.5).
Figure 116. Deterministic Latency State Machine in the Word Aligner
Parallel
Clock
From RX CDR
When using deterministic latency state machine mode, assert
rx_std_wa_patternalign
is complete. This is an edge-triggered signal in all cases except one: when the word
aligner is in manual mode and the PMA width is 10, in which case
rx_std_wa_patternalign
Figure 117. Word Aligner in Deterministic Mode Waveform
rx_std_wa_patternalign
rx_parallel_data
rx_patterndetect
Related Information
Word Aligner
2.8.2.1.1. Transmitter and Receiver Latency
The latency variation from the link synchronization function (in the word aligner block)
is deterministic with the
can use the
latency for port implementation in the remote radio head to compensate for latency
variation in the word aligner block. The
available to control the number of bits to be slipped in the transmitter serial data
stream. You can optionally use the
round-trip latency to a whole number of cycles.
® ®
Intel Arria 10 Transceiver PHY User Guide
282
Clock-Slip
Control
Deserializer
to initiate the pattern alignment after the reset sequence
is level sensitive.
rx_clkout
f1e4b6e4 b9dbf1db 915d061d
rx_errdetect
1101 0000 1010
rx_disperr 1101 0000 1010
0000
rx_syncstatus
0000
on page 485
rx_bitslipboundaryselectout
tx_bitslipboundaryselect
2. Implementing Protocols in Arria 10 Transceivers
Deterministic Latency
Synchronization State Machine
e13f913f 7a4ae24a bbae9b10 bcbcbcbc
1000 0010 1010 0000
1000 0000 1010 0000
1111
1111
port to fix the round trip transceiver
tx_bitslipboundaryselect
tx_bitslipboundaryselect
UG-01143 | 2018.06.15
To 8B/10B Decoder
95cd3c50 91c295cd
0000
port. Additionally, you
port is
port to round the