Intel Arria 10 series User Manual
  1. Manuals
  2. Brands
  3. Intel Manuals
  4. Motherboard
  5. Arria 10 series
  6. User manual

Intel Arria 10 series User Manual

Fpga hdmi design example
Hide thumbs Also See for Arria 10 series:
Table of Contents

Advertisement

Quick Links

Download this manual See also: User Manual
®
Intel
FPGA HDMI Design Example
®
User Guide for Intel
Arria 10
Devices
®
®
Updated for Intel
Quartus
Prime Design Suite: 17.1
Subscribe
UG-20077 | 2017.11.06
Send Feedback
Latest document on the web:
PDF
|
HTML

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Arria 10 series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for Intel Arria 10 series

Summary of Contents for Intel Arria 10 series

  • Page 1 ® Intel FPGA HDMI Design Example ® User Guide for Intel Arria 10 Devices ® ® Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe UG-20077 | 2017.11.06 Send Feedback Latest document on the web: HTML...

  • Page 2: Table Of Contents

    2.6 Design RTL Parameters..................36 2.7 Hardware Setup....................37 2.8 Simulation Testbench.................... 38 A Intel FPGA HDMI Design Example User Guide for Intel Arria 10 Devices Archives..41 B Revision History for Intel FPGA HDMI Design Example User Guide for Intel Arria 10 Devices....................... 42 ®...

  • Page 3: Arria ® 10 Devices

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 4: Intel ® Fpga Hdmi Design Example Quick Start Guide For Intel

    ® ® ® 1 Intel FPGA HDMI Design Example Quick Start Guide for Intel Arria 10 Devices UG-20077 | 2017.11.06 Figure 2. Directory Structure for the Design Example <Design Example> quartus simulation script software a10_hdmi2_demo.v build_ip.tcl db (Standard)/qdb (Pro) aldec tx_control_bsp a10_reconfig_arbiter.sv...
  • Page 5 ® ® ® 1 Intel FPGA HDMI Design Example Quick Start Guide for Intel Arria 10 Devices UG-20077 | 2017.11.06 Folders Files /mr_ce.v /mr_hdmi_tx_core_top.v /mr_tx_oversample.v i2c_master /i2c_master_bit_ctrl.v /i2c_master_byte_ctrl.v /i2c_master_defines.v /i2c_master_top.v /oc_i2c_master.v /oc_i2c_master_hw.tcl /timescale.v i2c_slave • (Intel Quartus Prime Standard Edition) /edid_ram.qsys...
  • Page 6 ® ® ® 1 Intel FPGA HDMI Design Example Quick Start Guide for Intel Arria 10 Devices UG-20077 | 2017.11.06 Folders Files reconfig_mgmt /mr_compare_pll.v /mr_compare_rx.v /mr_rate_detect.v /mr_reconfig_master_pll.v /mr_reconfig_master_rx.v /mr_reconfig_mgmt.v /mr_rom_pll_dprioaddr.v /mr_rom_pll_valuemask_8bpc.v /mr_rom_pll_valuemask_10bpc.v /mr_rom_pll_valuemask_12bpc.v /mr_rom_pll_valuemask_16bpc.v /mr_rom_rx_dprioaddr_bitmask.v /mr_rom_rx_valuemask.v /mr_state_machine.v /a10_hdmi2.sdc /mr.sdc /jtag.sdc Table 2.

  • Page 7: Hardware And Software Requirements

    ModelSim* - Intel FPGA Edition, ModelSim - Intel FPGA Edition Starter Edition, NCSim (Verilog HDL only), Riviera-Pro, or VCS/VCS-MX simulator 1.3 Generating the Design Use the Intel FPGA HDMI parameter editor in the Intel Quartus Prime software to generate the design examples. Figure 3.

  • Page 8: Simulating The Design

    1. Create a project targeting Intel Arria 10 device family and select the desired device. 2. In the IP Catalog, locate and double-click Intel FPGA HDMI IP Core. The New IP Variant or New IP Variation window appears. 3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip...

  • Page 9: Compiling And Testing The Design

    7. Connect RX (P2) of the Bitec HDMI 2.0 FMC Daughter Card (Revision 4) to an external video sink or video analyzer. 8. Ensure all switches on the development board are in default position. 9. Configure the selected Intel Arria 10 device on the development board using the generated file (Tools Programmer ).

  • Page 10: Design Limitation

    • Custom Development Kit: This option allows the design example to be tested on a third party development kit with an Intel FPGA. You may need to set the pin assignments on your own. Target Device Change Target Device...

  • Page 11: Intel Fpga Hdmi Design Example Detailed Description

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 12 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Figure 5. HDMI RX-TX Retransmit RX Top TX Top RX Core Top TX Core Top RX Core TX Core CPU Sub-System C Slave (EDID) RX Audio TX Audio Oversampler...

  • Page 13: Design Components

    If your design only requires HDMI TX or retransmitting HDMI stream from RX to TX through video frame buffer, supply the TX PLL reference clock directly from an external programmable oscillator. Intel recommends that you do not cascade IOPLL to TX PLL.
  • Page 14 5 and you can program the data width to support different number of symbols. For Intel Arria 10 devices, the supported data width is 20 bits for 2 symbols per clock. The extracted bit is accompanied by a data valid pulse asserted every 5 clock cycles.
  • Page 15 “permit_nf_pll_reconfig_out_of_lock=on” quartus.ini place in the file the Intel Quartus Prime project directory. You should see a warning message when you edit the IOPLL reconfiguration block (pll_hdmi_reconfig) in the Quartus Prime software with the Note: Without this...
  • Page 16 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Figure 7. Multi-Rate Reconfiguration Sequence Flow The figure illustrates the multi-rate reconfiguration sequence flow of the controller when it receivers input data stream and reference clock frequency, or when the transceiver is unlocked.
  • Page 17 Native PHY block according to the reset sequencing inside the block. output signal from this block also functions as a reset signal to tx_ready the Intel FPGA HDMI IP core to indicate the transceiver is up and running, and ready to receive data from the core. Transceiver Native PHY Hard transceiver block that receives the parallel data from the HDMI TX core and serializes the data from transmitting it.
  • Page 18 TX PLL The transmitter PLL block provides the serial fast clock to the Transceiver Native PHY block. For this Intel FPGA HDMI design example, fPLL is used as TX PLL. IOPLL Reconfiguration IOPLL reconfiguration block facilitates dynamic real-time reconfiguration of PLLs in Intel FPGAs.
  • Page 19 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Module Description For HDMI application, only RX initiates reconfiguration. By channeling the Avalon-MM reconfiguration request through the arbiter, the arbiter identifies that the reconfiguration request originates from the RX, which then gates...

  • Page 20: Dynamic Range And Mastering (Hdr) Infoframe Insertion And Filtering

    2.3 Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering The Intel FPGA HDMI design example includes a demonstration of HDR Infoframe insertion in a RX-TX loopback system. HDMI Specification version 2.0a allows Dynamic Range and Mastering InfoFrame to be transmitted through HDMI auxiliary stream.
  • Page 21 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Figure 9. RX-TX Link with Dynamic Range and Mastering InfoFrame Insertion The figure shows the block diagram of RX-TX link including Dynamic Range and Mastering InfoFrame insertion into the HDMI TX core auxiliary stream.
  • Page 22 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Control Signal Input HDMI TX Video Vsync. This hdmi_tx_vsync signal should be synchronized to the link speed clock domain. The core inserts the HDR InfoFrame to the auxiliary stream at the rising edge of this signal.

  • Page 23: Clocking Scheme

    Auxiliary Packet Generator altera_hdmi_aux_hdr.v 1'b0 from forming and inserting additional HDR Infoframe into the TX Auxiliary stream. 2.4 Clocking Scheme The clocking scheme illustrates the clock domains in the Intel FPGA HDMI IP core design example. ® ® Intel...
  • Page 24 TMDS clock frequency from the HDMI TX TMDS clock channel. For this Intel FPGA HDMI design example, this clock is connected to the RX TMDS clock for demonstration purpose. In your application, you need to supply a dedicated clock with TMDS clock frequency from a programmable oscillator for better jitter performance.
  • Page 25 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Clock Signal Name in Design Description TMDS Bit Clock Ratio Link Speed Clock Frequency TMDS clock frequency/ Symbol per clock TMDS clock frequency *4 / Symbol per clock TX/RX Video Clock Video data clock.

  • Page 26: Interface Signals

    Using Transceiver RX Pin as CDR Reference Clock • Using Transceiver RX Pin as TX PLL Reference Clock 2.5 Interface Signals The tables list the signals for the Intel FPGA HDMI IP core design example. Table 15. Top-Level Signals Signal...
  • Page 27 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 HDMI FMC Daughter Card Pins on FMC Port B Input HDMI RX I C SCL fmcb_la_tx_p_10 Input HDMI TX hot plug detect fmcb_la_tx_p_12 Inout HDMI I C SDA fmcb_la_tx_n_12...
  • Page 28 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 RX Reconfiguration Management • 0: No oversampling • 1: 5× oversampling Output RX reconfiguration management Avalon- reconfig_mgmt_write MM interface to transceiver arbiter Output reconfig_mgmt_read Output reconfig_mgmt_address Output reconfig_mgmt_writedata Input...
  • Page 29 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 HDMI RX Core Signals Output Note: N = symbols per clock ctrl Output locked Output vid_lock Input HDMI RX 5V detect and hotplug detect in_5v_power Inout hdmi_rx_hpd_n C Signals...
  • Page 30 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 TX Transceiver and IOPLL Signals Output TX Native PHY calibration busy signal to gxb_tx_cal_busy_out the transceiver arbiter Input Calibration busy signal from the gxb_tx_cal_busy_in transceiver arbiter to the TX Native PHY...
  • Page 31 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 HDMI TX Core Signals Input audio_data Input audio_info_ai Input audio_N Input audio_CTS Input audio_metadata Input audio_format Output HDMI TX core auxiliary interfaces aux_ready Input aux_data Input aux_sop Input aux_eop...
  • Page 32 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Table 18. Transceiver Arbiter Signals Signal Direction Width Description Input Reconfiguration clock. This clock must share the same clock with the reconfiguration management blocks. Input Reset signal. This reset must share the...
  • Page 33 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Signal Direction Width Description Input Calibration status signal from the TX tx_cal_busy transceiver Output Calibration status signal to the RX rx_reconfig_cal_busy transceiver PHY reset control Output Calibration status signal from the TX...
  • Page 34 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Signal Direction Width Description Input rx_aux_data Output HDMI TX video interfaces hdmi_tx_de Note: N = symbols per clock Output hdmi_tx_hsync Output hdmi_tx_vsync Output N*48 hdmi_tx_data Output HDMI TX audio interfaces...
  • Page 35 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Signal Direction Width Description Output oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_writedata Input oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_waitrequest Output oc_i2c_master_av_slave_translator_avalon_an ti_slave_0_chipselect Output EDID RAM access edid_ram_access_pio_external_connection_exp interfaces. Assert Output edid_ram_slave_translator_address edid_ram_access_pio_ external_connection_ Output edid_ram_slave_translator_write when you want to...

  • Page 36: Design Rtl Parameters

    Use the HDMI TX and RX Top RTL parameters to customize the design example. Most of the design parameters are available in the Intel FPGA HDMI Design Example parameter editor. You can still change the design example settings you made in the parameter editor through the RTL parameters.

  • Page 37: Hardware Setup

    2.7 Hardware Setup The Intel FPGA HDMI design example is HDMI 2.0 capable and performs a loop- through demonstration for a standard HDMI video stream. To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the Transceiver Native PHY RX block, and the HDMI sink...

  • Page 38: Simulation Testbench

    1 = All 3 channels locked USER_LED[3] RX oversampling status. • 0 = Non-oversampled (data rate > 1,000 Mbps in Intel Arria 10 device) • 1 = Oversampled (data rate < 100 Mbps in Intel Arria 10 device) USER_LED[4] TX HDMI PLL lock status.
  • Page 39 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Figure 11. Intel FPGA HDMI IP Core Simulation Testbench Block Diagram CRC Check Video data Video TPG CRC Check Audio data Audio Sample Gen HDMI TX HDMI RX Audio Data Check...
  • Page 40 2 Intel FPGA HDMI Design Example Detailed Description UG-20077 | 2017.11.06 Table 25. Intel FPGA HDMI Design Example Supported Simulators Simulator Verilog HDL VHDL ModelSim - Intel FPGA Edition/ ModelSim VCS/VCS-MX Riviera-Pro NCSim ® ® Intel FPGA HDMI Design Example User Guide for Intel...

  • Page 41: A Intel Fpga Hdmi Design Example User Guide For Intel Arria 10 Devices Archives

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

  • Page 42: B Revision History For Intel Fpga Hdmi Design Example User Guide For Intel Arria 10 Devices

    Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 43 B Revision History for Intel FPGA HDMI Design Example User Guide for Intel Arria 10 Devices UG-20077 | 2017.11.06 Date Version Changes • Added a link for workaround to avoid jitter of PLL cascading or non- dedicated clock paths for Intel Arria 10 PLL reference clock.

Table of Contents